JVC XV-M565BK - Page 57

XV-M565BK/M567GD
1-57
I/O
I/O
I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
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I/O
O
O
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O
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O
O
O
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O
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O
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O
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O
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51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
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98
43
44
45
46
47
48
49
50
Connected to TP558
Connected to TP559
Connected to TP560
Connected to TP561
3.3-V supply voltage for I/O signals.
Connected to TP562
Ground for core logic and I/O signals.
Connected to TP563
Connected to TP564
Programmable I/O pins. Input mode after reset
Memory data
Memory data
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
2.5-V supply voltage for core logic.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for I/O signals.
SDRAM write enable. Decoder asserts active LOW to request a write operation to the
SDRAM array.
Ground for core logic and I/O signals.
SDRAM system clock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for I/o signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
2.5-V supply voltage for core logic.
Connected to TP511
Ground for core logic and I/O signals.
Connected to TP512
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
Pin No.
Symbol
ARAM ADDR8
ARAM ADDR9
ARAM ADDR10
ARAM ADDR11
E VDD
ARAM ADDR12
E VSS
ARAM ADDR13
ARAM ADDR14
TEST PIN1
M DATA 1 5
M DATA 0
E VDD
M DATA 1 4
E VSS
M DATA 1
M DATA 1 3
M DATA 2
E VDD
M DATA 1 2
E VSS
M DATA 3
i vdd
M DATA 1 1
i vss
M DATA 4
E VDD
M DATA 1 0
E VSS
M DATA 5
M DATA 9
M DATA 6
E VDD
M DATA 8
E VSS
M DATA 7
LDQM
UDQM
E VDD
MWE
E VSS
SD CLK
SD CAS
SD RAS
E VDD
SD CS1
E VSS
SD CS0
i vdd
EDO CAS
i vss
EDO RAS
E VDD
MADDR 9
E VSS
MADDR 11
I/O
Function
ZIVA3-PEO (2/5)