The remaining portion of the analog circuitry produces the
selectable compliance voltage limit. An 8 bit digital-to-
analog converter (DACl U308 starts this process. With 128
combinations, each step is scaled to represent one volt of
compliance. Since U308 is a current output DAC, U309 is
required to revert back to a voltage level. The output of
U309 then represents the selected compliance voltage
scaled down by a factor of 20.
This signal and its inverse fU309A. R324 and R327l are
applied to divider network R331 and R336 which are refer-
enced to output common, At the junction of each divider
network is an amplifier which reverses the previous scaling
factor. Resulting from this is an error voltage approximately
equal to the difference between the actual compliance volt-
age level and the programmed level. Each amplifier U307A
and B and the associated circuitry, is coupled through
diodes CR303 and CR302 on R333. The polarity of the
diodes is arranged such that a voltage is impressed on R333
only when the actual voltage compliance exceeds + i- the
programmed value. This result is applied to the output node
via low leakage diode CR304 preventing any further com-
pliance voltage excursion. Current from the range resistors
is shunted through diodes CR305 end CR306 when this
operation limit occurs. Resistors R330 and R332 add an off-
set to compensate for diode drops in CR302 through
CR304.
The circuit configuration of U313A and B comprise a win-
dow comparator to detect a V-limit condition across R333.
The comparator limits are set by resistor divider network
R338 through R341. U313A and B open collector outputs
are configured in a “wire ORed” fashion through pull up
resistor R346. Whenever the voltage across R333 exceeds
the comparator limits, a logic 1 is developed through current
limiting resistor R347 to the output of inverter U316E. C311
is used for stabilization.
VR301 supplies the digital circuitry with the required + 5V.
This voltage is also supplied to the digital board for use by
the ooticallv isolated portion of the circuitry.
4.5 DIGITAL BOARD (Microcomputer)
To facilitate understanding of the following discussion refer
to schematic diagram 220-106 (sheet I of 2). For an overall
block diagram of the digital circuitry refer to Figure 4-2.
The microcomputer and its associated logic circuitry, con-
trols front panel functions (source, dwell time, program
control etc.), operation of the front panel display and data
through the IEEE-488 interface circuitry.
dress lines A13, Al4 and A15; UllO sections the 64k of
memory space into 8k end 4k segments. The total memory
used is a small portion of the entire addressing capabilities
of the 6808 microprocessor U115. Memory locations for the
64k addresses are assigned the values 0000,s through
FFFF,,.
Interfacing of the microprocessor with the RAMS. ROMs.
Front Panel, VIA or the IEEE-488 interface is controlled by
the address decoder, UI IO.
Partial address decoding is used in this system. The function
selected is determined by the state of the address lines A13,
AI4 and A15. These address lines determine which output is
selected at the decoder UlIO in accordance with the
memory map. Only one of the devices (RAM, ROM, VIA,
etc.1 will have access to the data bus at any time. The ed-
dress decoder selects one of the devices only after a Valid
Memon/ Address VMA has been asserted et the decoders
input EN (pin 61. The VMA signal is generated by the 6808
microprocessor.
Timing for the computing sequence is provided by the
4MHz crystal YlOl. The 6808 microprocessor divides this
signal by four to produce a 1MHz signal at the a2 output
(pin 37).
U102, U104, UlOK, U108C and their associated circuitry,
forms a reset network (watchdog) which resets the micro-
processor, VIA and the IEEE-488 interface. The circuit
actuates in the event the front panel display is not updated
after a specific period of time has elapsed due to a lost pro-
gram or power line transient.
The digital circuitry is optically isolated from the analog cir-
cuitry by AT101 through AT104, U113A, B, U117 and their
associated circuitry. The output signals consist of latch,
clock and data out. These signal lines permit serial com-
munication to the analog circuitn/. The data in signal line is
received from the analog circuitry and is either the recircu-
lated data or the overcompliance (V-limit) data depending
on the state of the latch line. When the latch line is a logic 1,
the data in line will represent the compliance state (logic 1
implies an overcompliance or V-limit). When the latch line is
a logic 0. the data in line will be the recirculated data sent
out to the analog side as data out. This data is inverted on
the digital side of the isolation.
The remaining circuitry on the digital board consists of ex-
ternal trigger inputs and outputs. C123, CRI12, CRlIl,
R121 and R128 comprise an input protection network for
trioaerino inout to PB6 of the VIA KJI14l. VlI3D. CR109.
The microcomputer includes a 6808 microprocessing unit
CRilO, 6127 and R122 buffer a triggered output originated
UI15; a 6522 versatile interface adapter UI14; two 2732
on PB3 of the VIA fU114l.
ROMs U109 and Ulll; four 2114 RAMS UlOl, U103, U105 4.6 DISPLAY ClRCUlT
and U107; an address decoder UllO: a data busdriverU116
end the necessary reset logic. The memory utilized in this
system is shown in the memory map (Figure 4-3). Using ad-
The display information is outputted on PA0 through PA7
on the VIA 11/O) bus. The information is updated at a 1kHz
44
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