Lexicon MPX-1 User Manual

flop XFER will set. XFER will enable the Tri-State buffer (U39) which drives the
S-100 bus .p" or processor control lines. At this timet the bus CPU is also
driving the same lines. It is very important that both devices drive the lines
in exactly the same directions as described by the 8-100 bus specifications. The
same
IC will also assert the disable lines ADSB*t SOSB* and OOOSB* which disable
the CPU address
t
status and data output drivers respectively.
At the next rising edge of the bus clock
t
the signal Bus Cycle (BG) will
set. Be enables the MPX drivers for the address
t
status and data output busses.
It also causes Command Disable (CDSB*) to be asserted
t
turning off the CPU bus
drivers for the processor control lines. This overlap in drive on the control
bus is necessary to prevent spikes on the active high strobe signals.
The signal BC brackets the MPX cycle on the external bus. The signal pSYNC
will go high for the first "T" state with pSTVAL* going low for the second half
of p8YNC. The status which is asserted is determined by the 8085 cycle which is
still held in a wait. An appropriate 8-100 status is decoded for I/O or memory
cycles (including MI cycles) and asserted for the entire cycle. The twenty-four
bit extended address is made up of two sections. The high order sixteen bits are
driven from registers which are writable at memory locations decoded by the
LS138 (U48). The least significant eight bits are taken directly taken from the
8085 address latch. For memory operations
t
the two address latches define a 256
byte "window" which may be accessed by the 8085. For I/O operations
t
the port
address is asserted directly from the address latch. Since the high order ad-
dress byte may be software controlled by writing to the latch
t
the 8085 may
simulate zao or 16 bit CPU I/O instructions. The address is also asserted for
the duration of BC.
At the end of the first "T" state which is signalled by the next rising
edge of the bus clock
t
STB ENA will set inhibiting pSYNC and enabling the bus
strobe. Either pDBIN or pWR* wtj.l be decoded, again depending on the state of
the waiting 8085. At this same edge of the clock
t
the bus signals ROY and XRDY
are sampled. If either signal is false
t
an additional strobe (wait) state will
follow.
At the end of a strobe state which began with the ready lines high
t
SIB INH
will be set. This terminates the strobes providing one "T" state of hold time.
At the next clock
t
the presence of STB INH will clear BC. Be low wi th STB
ENA still active will generate RELEASE. RELEASE clears I WANT which then clears
APRIO. The absence of BC marks the start of the bus transfer back to the CPU.
All of the MPX bus drivers except for the control bus are disabled and the CPU
control bus drivers are enabled providing the overlap period.
At the next falling edge of the clock
t
APRIO being low will cause XFER to
clear
t
inhibiting the control bus driver. This completes the DMA cycle as seen
from the bus however it is not until the following rising edge of the clock that
BC being low clears STB ENA. The falling edge of SIB ENA sets END WAIT which
will release the 8085. If the 8085 had been in a memory or I/O write eyelet its
data has already been transferred. If a memory or I/O read had been performed
t
the data receive~ from the bus has been latched by the end of the bus strobe and
is available to be accepted by the 8085 from the MPX internal data bus.
One
more clock is required with STB ENA low to clear STB INH. This com-
pletes the OMA cycle returning all of the DMA hardware to its initial state.
32

Lexicon MPX-1 Specifications

General

Brand	Lexicon
Model	MPX-1
Category	Recording Equipment
Language	English