Lexicon MPX-1 User Manual

The MPX may also communicate with the S-100 bus as a temporary master. As
the name implies, the bus CPU or permanent master will give up the bus for a
short time allowing a temporary master to take control. The protocol for trans-
fer of the bus as defined in the IEEE 696/S-100 specification must be carefully
adhered to if proper operation is to be obtained. Once the bus is obtained, the
temporary master will generate all of the bus signals usually provided by the
CPU (with the exception of INTA cycles or releasing the bus to other temporary
masters).
The MPX will perform a DMA cycle if either a memory address in the range of
COOO - FFFF is accessed or an I/O port is accessed. Since there are no port
addresses used on the MPX, all port accesses must be external. The signal
External Enable (EXT ENA) is generated on EXT MEM which was decoded from the
high order address lines or on I/O status and not interrupt acknowledge. EXT ENA
will assert a false level on the 8085 RDY line making the 8085 hang in a wait.
If EXT ENA (which was decoded entirely from status signals) has remained until
the leading edge of the 8085 strobe, the flip-flop I WANT will be set. When the
bus is available as determined by the signals HOLD* and Hold Acknowledge (pHLDA)
both being inactive, I WANT will set Assert Priority (APRIO). APRIO will assert
HOLD* and enable the priority arbitration logic.
Priority arbitration is handled by the three ICs U33,34 and 35. The 5-100
bus DMA address bus consists of four open collector lines which are active low.
To understand this process, consider the arbitration of the most significant bit
DMA3*. If a device has set APRIO and the most significant bit of its priority is
a "1", it will assert DMA3* by pulling the line low. If a different device also
has APRIO set, but the most significant bit of its priority is a "0", its open
collector output will be unable to pull DMA3* high. Based on consideration of
this single bit, the second device will see that some device on the bus has a
priority bit of "I" where he has a "0" and will know that he is not the hibhest
priority device on the bus at this time. The first device on the other hand will
see his own address bit ass~ted and know that he is the highest priority device
(based on consideration of this single bit only).
If a device has asserted a given bit of his priority and there are no other
devices asserting a higher priority in that bit, it may enable the next most
significant bit. The operation of the bits is cascaded. In a finite amount of
time, the address of the highest priority device will have stabilized on the DMA
address lines. The device asserting the least significant bit and not finding a
higher priority bit on the least significant address line will generate the
signal IMHI.
The
time required for the arbitration to settle is provided by the bus CPU
sensing the HOLD* line one "T" state before acknowledging the bus. This scheme
would
not work if additional devices could enter the arbitration just prior to
the CPU asserting pHLDA, but this may not happen because a device asserts HOLD*
once it sets APRIO. HOLD* will lockout other devices by preventing them from
setting APRIO. Arbitration really only occurs when two devices set APRIO almost
simultaneously.
On receipt of pHLDA, a device will clear APRIO if IMHI is false. If, on the
other hand, the device had the highest priority, APRIO will remain set and the
control of the bus will be received. This operation procedes as follows:
At the falling edge of the bus clock following pHLDA, the transfer flip-
31

Lexicon MPX-1 Specifications

General

Brand	Lexicon
Model	MPX-1
Category	Recording Equipment
Language	English