Lexicon MPX-1 User Manual

clear a counter (US) which in turn generates INIT. INIT is "OR"ed with address
line A14 (U2l) so that memory accesses in the range of 0000 to 3FFF will actual-
ly access 4000 to 7FFF when INIT is active. The initial instruction fetch by the
8085 will actually come from location 4000 which is the start of the ROM. The
I.IV,') ,-- .. '"'~ .. " t-,,<I 1 .. t-::lTt of the code) at this location.
The LS138 one of eight decoder (U48) decodes the three low order address
lines (AO - A2) qualified by Internal Strobe (INT STB) described above to obtain
Interrupt Controller Enable (INT CTL ENA), Set Interrupt (SET INT), Interrupt
Acknowledge Strobe (INTA STB), A8-lS STB and A16-23 STB making all of these
facilities memory mapped within the 8000 to BFFF range. The INT CTL ENA is
generated for a pair of addresses as required for programming the 8259A as
described above.
An 8-100 bus I/O port with a switch selectable address is decoded by the
LS2521 (U41). No data is accepted by this port, however writing to the port will
generate an attention signal (ATTN) to the 8085 by causing RST7.5 to be
asserted.
Two methods are provided for the MPX to call the bus CPU. The SET INT
signal described above may set a latch (U24). The output of the latch is buf-
fered (U25). It may be jumpered to any of the S-100 interrupt lines, including
NMI and INT. The latch is cleared by an interrupt acknowledge cycle on the S-100
bus which is decoded by (U7). The other CPU call option uses the 8085 Serial
Output Data line (SOD). The buffered SOD output (U25), may also be jumperc:d to
any of the S-100 bus interrupt lines.
For environments where the MPX is the only interrupt controller in the
system, the MPX may provide a single byte response to the CPU interrupt acknow-
ledge cycle which results from a call by the MPX to the bus CPU. (This response
would normally be a RST instruction for 8080 type CPUs, or vector information
for 8086/88 or 68QOO type processors). Another of the addresses decoded by the
LS138 is INTERRUPT RESPONSE. The resulting strobe loads an eight bit latch with
the contents of the data bus. The buffered latch will enable its outputs onto
the S-100 01 bus during a bus interrupt acknowledge cycle if the interrupt
response enable switch is on.
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Lexicon MPX-1 Specifications

General

Brand	Lexicon
Model	MPX-1
Category	Recording Equipment
Language	English