Lexicon MPX-1 User Manual

MPX - THEORY OF OPERATION
The MPX is designed around the Intel 8085 microprocessor. In this applica-
tion, the 8085 may access resources which are local to the MPX wi thout use of
the S-100 bus. Resources external to the MPX may be accessed through a temporary
mast:.er_interfactL-llS d_ef_ined in _the IEEE 696/S-100 sDecification.
,
and INT STB (INT for Internal) which is decoded for 8000 through BFFF.
The RAM consists of either eight 2147 or 2167 type ICs (U10-U17) which are
each either 4K or 16K by 1 bit. The high order address inputs A8-A11 come
directly from the 8085 while the lower eight lines come from the address latch
described above. The data input and data output lines of each IC are tied
together to provide a bidirectional connection to the internal data bus. The
remaining inputs are Chi~ Enable (CE) which is driven by the RAM STB as de-
scribed above and Write Enable (WE) which is controlled by 8085 81 line. If WE
is false, CE will cause the contents of the addressed location to be driven onto
the data bus. If WE is true, the memory outputs are forced to their high Z
state. CE will cause the data on the bus to be written at the addressed
location.
ROM storage is provided by a 2716, 2732 or 2764 EPROM. The ROM STB de-
scribed above is used to drive the Output Enable (DE). A ROM ENA signal is
derived from address and status information (without strobes) by a decoder
(U32). This "look ahead" signal is used to drive Chip Enable CE of the R01'1 and
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Lexicon MPX-1 Specifications

General

Brand	Lexicon
Model	MPX-1
Category	Recording Equipment
Language	English