fi;ure
5.
108618088 Interrupt Vector Teble
When the
BOB6/808B
receives
an
Interrupt vector byte
from the S259A. It
mulllplles
Its value by four to acquire
the address of the Interrupt type For example
If the
interrupt·vector byte specifies type
128
(80H
I the
vec
tored address in
80B6/80B8
memory
IS
4 x
SOH
WhiCh
equals 200H. Program execution
IS
then vectored
to
the
service routine whose address is specified by the code
segment and
instruction
pointer values Wlth,n type
128
located at 200H. To show
how
this
IS
done. let's assume
interrupt
type
12S
is to vector data to 8086/B088 memory
location
2FF5FH. Figure 6 shows
two
pOSSible
ways to
set values
of
the code segment and Instruction pOinter
for vectoring to location 2FF5FH, Address generation
by the code segment and
instruction
pointer is
ac-
complished
by an
offset
(they overlap).
Of
the total
20·bit address capability. the code segment can deSig-
nate the upper
16
bits, the
instruction
pOinter can
deSignate the lower
16
bits,
data
bus.
Not
used as a direct address,
this
interrupt-
vector
byte pertains
to
one
of
256
interrupt
"types"
sup-
ported by the
BOB6/BOB8
memory. Program executIOn is
vectored
to
the corresponding service routine by the
contents
of
a specified interrupt type.
All
256
interrupt types are located in absolute memory
locations 0
through
3FFH which make up the
B0861
80BB's interrupt·vector table. Each type in the interrupt-
vector table requires 4 bytes
of
memory and stores a
code segment address and
an
instruction
pointer ad-
dress. Figure 5 shows a
block
diagram of the interrupt-
vector table. Locations 0 through 3FFH should be
reserved for the interrupt·vector table alone. Further·
more, memory locations 00 through 7FH (types 0-31) are
reserved
for
use by Intel Corporation for Intel hardware
and software products. To maintain
compatibility
with
present and future IIltel products, these locations
should not be used
tents
of
the program counter back
off
the
stack
to
resume program
execution
where
it
left
off.
Note,
that
because
interrupts
are disabled during the
interrupt
acknowledge sequence. the
EI
instruction
must
be
executed
either
during
the service
routine
or
the
main
program before further
interrupts
can be processed.
For
additional
information
on the
8OS0A
interrupt
struc·
ture and operation, refer
to
the
MCS·SO
User's Manual.
1.3 MCS·86188™_8259A OVERVIEW
Operation
of
an MCS-S6/S8-8259A
configuration
has
basic
similarities
of
the MCS·BO/B5-8259A configura·
tions. That is. a device can cause an interrupt by
pulling
one
of
the B259A's interrupt request pins (IRO-IR7) high.
If the S259A honors the request,
its
INT pin
will
go
high,
driving the
SOS6/S0SS's
INTR pin high, Like the
SOSOA
and
SOB5A,
the INTR pin
of
the
SOB6/BOSB
is asynchro-
nous,
thus
it
can receive
an
interrupt
any time, The
80B6/S0BB
can also accept or disregard requests on
lNTR under software control
using
the
STI
(Set Interrupt)
or
CLI (Clear Interrupt)
instructions.
These
instructions
set or clear the interrupt·enabled flag IF, Upon
8086/BOSS
reset the IF flag is cleared,
disabling
external
interrupts
on lNTR. Beside the INTR pin, the 8086/808S
provides
an
NMI (Non-Maskablt! Interrupt) pin. The NMI
functions
similar
to the
SOS5A's
TRAP;
it
can't
be dis-
abled or masked. NMI has higher
priority
than INTR.
Although
there are
some
basic similarities,
the
actual
processing
of
interrupts
with
an
8086/80SS is
different
than an 8080A
or
B085A. When an interrupt request is
present and interrupts are enabled, the
80B6IBOSB
enters
its
interrupt
acknowledge machine cycle. The interrupt
acknowledge machine
cycle
pushes the flag
registers,
onto
the
stack
(as in a PUSHF instruction),
It
then clears
the
IF
flaQ
which
disables interrupts. The contt!;nts
of
both
the code
segment
and the
instruction
pointer
are
then
also
pushed
onto
the stack. Thus, the stack retains
the
pre·
interrupt
flag
status
and pre-interrupt program
location
which
are used
to
return from
the
service
routine, The
808618088
then issues the
first
of
two
INTA
pulses
which
signal the B259A that the
BOB6/S0BB
has
honored
its
interrupt
request.
If
the
BOB6/BOB8
is used in
its
"MIN
Mode" the INTA Signal
is
available from the
B086/B08B
on
its
INTA pin. If the
B086/BOSS
is
used in the
"MAX
Mode"
the INTA signal is available via the
82BB
Bus
Controller
INTA pin. Additionally, in the
·"MAX
Mode"
the
BOB6/BOBB
LOCK pin goes
low
during
the in-
terrupt
acknowledge sequence. The LOCK
signal
can be
used to
indicate
to
other
system
bus
masters not
to
gain
control
of
the
system
bus
during
the
interrupt
acknowl·
edge sequence. A
"HOLD"
request
won't
be honored
while
LOCK is iow.
The 8259A is
now
ready
to
vector program
execution
to
the
corresponding service routine. ThiS
is
done during
the sequence of the
two
INTA pulses issued by the
80B6/
80S8.
Unlike operation
with
the
SOBOA
or
80B5A,
the
8259A
doesn't
place a CALL
instruction
and the
starting
address
of
the service routine on the data bus. Instead.
the
first
INTA pulse is used only
to
signal the 8259A
of
the honored request. The second INTA pulse causes the
B259A
to
place a single interrupt·vector byte
onto
the
36
-
INTERRUPT TYPE 255
INTERRUPT TYPE 250
•
•
•
INTERRUPT TYPE 2
INTERRUPT TYPE I
INTERRUPT TYPE 0
3FFM
3FCM
3FBM
3F801
B01
8M
701
001
301
001
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