es
IMSBI
1-
__
--:2~0;.c.H
-I'FFH
eSCLSBI
OOH
'FEH
IP
IMSB)
1----'-FF'--H-----l,FDH
IPCLSB)
SFH
'FCH
changes in the service routine. Note especially thaI this
includes the state of the IF flag. thus interrupts are
reo
enabled automatically when returning from the service
routine.
Beside external interrupt generation from
the INTR Pin.
the 8086/8088 is also able to invoke interrupts
by
soft·
ware. Three interrupt instructions
are
provided: INT. lNT
(Type
3),
and INTO. INT is a two byte instruction the sec·
ond byte selects the interrupt type. INT (Type
3)
IS a one
byte instruction which selects interrupt Type 3 INTO
IS
a conditional one byte interrupt Instruction which
selects interrupt Type 4
if
the
OF
flag (trap
on
overflow)
is set. All the software interrupts vector program
execu·
tion
as
the hardware interrupts do
TYPE
'28
TYPE
128
FFH
FEH
FDH
,FCH
2FH
,
FOH
,
OOH
,
SFH
-
eSIMSB)
eSH.SBI
IPIMSB)
IPClSBI
Figure
6.
Two
hamp'e.
ot
808618088
Interrupt
T,pe
128
Vectoring
to Location 2FFSFH
For further information on 8086/8088 interrupt operation
and internal interrupt structure refer
to
the MCS·86
User's Manual and the
8086
System Design application
note.
When entering
an
interrupt service routine, those regis·
ters that are mutually used between the main program
and service routine should be saved.
The
best
way
to do
this is to :'PUSH" each register used onto the stack im·
mediately. The service routine can then "POP" each
register
off
the stack in the same order when it
IS
com·
pleted.
Once the service routine is completed the main program
may
be
re-entered
by
using a
IRET
(Interrupt Return) in·
struction. The IRET instruction will pop the pre·interrupt
instruction pointer, code segment and flags
off
the
stack. Thus the main program will resume where it was
interrupted
with
the same flag status regardless of
2.
8259A FUNCTIONAL BLOCK DIAGRAM
A block diagram
of
the 8259A is shown in Figure
7.
As
can
be
seen from this figure, the 8259A consists of eight
major blocks: the Interrupt Request Register
(IRR),
the
In-Service Register (lSR), the Interrupt Mask Register
(IMR), the Priority Resolver
(PR),
the cascade bufferl
comparator, the data bus buffer, and logic blocks for
control and read/write. We'll first go over the blocks
directly related to interrupt handling, the IRR,
ISR,
IMR.
PR,
and the control logic. The remaining functional
blocks are then discussed.
PIN CONFIGURATION
BLOCK DIAGRAM
'NT
1
IRQ
.AI
NTEAAUPT
'A2
REQUEST
_-IA)
REG
IR.
IIARt
_tR~
~IR6
L-.-,-_.r--,A7
PRIORITy
(SOLvER
CONTROL
LOGIC
IN
SERVICE
AEG
IISRI
INtERNAL
BUS
,
I
I
I
I
U
DATA
IUS
IUfFER
AD
Wii
READf
WRITE
LOGIC
....
Cs
C
...
SO
CAS
I
CASl
PO,EN
a
Vee
iiii
Ae
"'"''1'
iiO
INTA
0,
1117
D.
Illtl
Os
1115
D.
Ill.
0
3
1113
D~
1112
0,
Ill'
Do
IRD
CAS 0
INT
CAS'
!P'/[N
GND CAS2
PIN NAMES
0
,
,0
0
DATA
BUS
IBI·DIRECliONAU
RD
READ
INPUT
WR
WRITE
INPUT
...
COMMAND
SELECT ADDRESS
cs
CHIP
SELECT
C
...
Sl·CASD
CASCADE
LINES
.
P,N
SLAVE
PRDGRAMIENABLE BUFFEIl
INT
INTERRUPT OUTPUT
INTA
INTERRUPT
ACKNOWLEDGE
INPUT
IRO·IRl
INTERRUPT REOUEST INPUTS
Figure
7.
1258A BloCk Diagram end
Pin
Conllguretion
37
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