2.1
INTERRUPT REGISTERS AND CONTROL LOGIC
Basically, interrupt requests are handled by three "cas-
caded"
registers: the Interrupt Request Register (IRR) is
use
to
store all the interrupt levels requesting service;
the In-Service Register (ISR) stores all the levels
which
are being serviced; and the
Interrupt
Mask Register
(IMR) stores the
bits
of
the
interrupt
lines
to
be masked.
The Priority Resolver
(PR)
looks at
the
IRR, ISR and IMR,
and determines whether an INT should be issued by the
the
control
logic
to
the processor.
Figure
8 shows conceptually how
the
Interrupt Request
(IR)
input
handles
an
interrupt
request and how the
various
interrupt
registers interact. The figure repre-
sents one of eight
"daisy·chained"
priority
cells. one for
each
IR
input.
The best way
to
explain the operation of the
priority
cell
is
to
go through the sequence
of
internal events that
happen when
an
interrupt request occurs. However.
first, notice
that
the input
circuitry
of
the
priority
cell
allows
for both level sensitive and edge sensitive
IR
in·
puts. Deciding
which
method to use
is
dependent on the
particular
application
and
will
be
discussed
in more
detail later.
When the
IR
input
is
in
an
inactive state (LOW). the edge
sense
latch
is
set. If edge sensitive triggering is
selected, the
"a"
output
of the edge sense latch
will
arm the input gate
to
the request latch. This input gate
will
be disarmed after the
IR
input goes active (HIGH)
and the interrupt request has been acknowledged. This
disables the input from generating any further Inter·
rupts
until
it
has returned low
to
re·arm the edge sense
latch.
If
level sensitive triggering is selected, the "a"
output
of
the edge sense latch is rendered useless This
means the level
of
the IR input is in complete control of
interrupt generation; the input won't be disarmed once
acknowledged. .
When an interrupt occurs on the
IR
input,
it
propagates
through the request
I~tch
and
to
the
PR
(assuming the
input
isn't
masked). The
PR
looks at the incoming
reo
quests
and the currently in·service interrupts to ascer·
tain whether an interrupt should be issued to the proc·
essor. Let's assume that the request
is
the only one in·
coming
and no requests are presently in service. The
PR
then causes the control logic to pull the INT line
to
the
processor high.
LTI'"
BIT
O-lDGE
,.
LEVEL
I
TO OTHER PRIORITV CELLS
I I
Nons
1
"ASTER
CLEAR ACTIVE
ON,V
DURING
ICW'
2
FREEZE,.S
ACTIVE DURING 'NTAI AND POLL
SEOUENClS
ONLY
3 TRUTH TABLE FOR D·lATCH
TIi-t
D
I)
IQPERATION
, Di
I)j
FOLLOW
o •
Qft-'
I HOLO
Flgur.'.
P"orily
C.II
When the processor honors the INT pulse,
it
sends a se-
quence
of
INTA pulses
to
the 8259A (three
for
8080Al
8085A,
two
for
808618088).
During
this
sequence the
state of the request latch
is
frozen (note the INTA.freeze
request timing diagram). Priority
is
again resolved by the
PR
to determine the appropriate interrupt vectoring
which is conveyed
to
the processor via the data
bus
38
Immediately after the interrupt acknowledge seQuence,
the
PR
sets the corresponding
bit
in the ISR which
simultaneously clears the edge sense latch
If
edge sen·
sitive triggering is used, clearing the edge sense latcn
also
disarms the request latch. This ,nhlblls the
POSSll)lllty of a
still
active
IR
Input from propagating
througn the priority cell The
IR
Input must return 10
an
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