inactive state. setting the edge sense latch, before
another interrupt request can be recognized. If level sen·
sitive triggering is used, however, clearing the edge
sense latch has no
affect
on the request latch. The state
of the request latch
is
entirely dependent upon the
IR
in·
put
level. Another interrupt will be generated immedi·
ately
if
the
IR
level is left active after its
ISR
bit has been
CASO- 12,13,
CAS2
15
§P/EN
16
1/0
Cascade
Lines:
The CAS lines form a
private 8259A bus
to
control a multi-
ple 8259A structure. These pins
are
outputs for a master 8259A and in·
puts for a slave 8259A.
1/0 Slave
Program/Enable
Buffer:
This is
a
dual
funr..tinn
nin
WhQn
in
+h.a.
n.llf_
are located in
this
block. The
RD,
Wl1,
AU,
and
CS
pins are used
to
control access to
this
block by the
processor.
Cascade BufferlComparator
As mentioned earlier,
multiple
8259A's can be combined
to expand the number of interrupt levels. A master·slave
relationship
of
cascaded B259A's is used for the expan·
sion. The SP/EN and the CASO-2
pinsllre
used for oper·
ation
of
this block. The cascading
of
8259A's is covered
in depth in the "Operation of the 8259A" section of this
application note.
AO
27
by a sequence
of
interrupt acknowl·
edge pulses issued by the CPU.
AO
Address
Line:
This pin acts in con·
junction
with the
CS,
WR,
and
RD
pins. It is used by the 8259A
to
de·
cipher between various command
words the
CPU
writes and status the
CPU
wishes
to
read,
It
is typically
connected
to
the
CPU
AO
address
line
(A
1 for 8086/8088),
2.3
PIN FUNCTIONS
Name
Pin"
1/0 Function
WR
2
3
3.
OPERATION OF THE 8259A
Interrupt operation
of
the 8259A falls under five main
categories: vectoring, priorities, triggering, status, and
cascading. Each
of
these categories use various modes
and commands. This section will explain the operation
of
these modes and commands. For clarity
of
explana·
tion, however, the actual proQramming
of
the 8259A isn't
covered in this section but in "Programming the 8259A".
Appendix A is provided as a cross reference between
these two sections,
3.1
INTERRUPT VECTORING
Each
IR
input
of
the 8259A has
an
individual interrupt·
vector address in memory associated with it. Designa-
tion
of
each address depends upon the initial program·
ming
of
the 8259A.
As
sl'Bted earlier, the interrupt
sequence and addressing of an MCS·80 and
MCS-B5
system differs from that
of
an
MCS·86 and MCS-88
system, Thus, the 8259A must
be
initially programmed
in either a MCS-80/85 or MCS-86/88 mode
of
operation
to
insure the correct interrupt vectoring.
+
5V
supply
Ground
Chip Select: A low on
this
pin
en-
ables
RD
and
WR
communication be·
tween the
CPU
and the 8259A. INTA
functions are independent
of
es.
Write: A low on this pin when
CS
is
low enables the 8259A to accept
command words from the
CPU.
React:
A low on this pin when
CS
is
low enables the 8259A
to
release
status
onto
the data bus for the
CPU.
I/O
Bidirectional
Data Bus:
Control,
status and interrupt-vector informa·
tion is transferred via thiS bus.
28
14
07-00
4-11
Vee
GNO
CS
39
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