07
De
05
04
03
02
01
DO
IA7
T7
T6
Tfi
T4
T3
1 1
1
IA6
T7
T6 T5
T4
T3
1 1
0
IRS
T7
TS
T5
T4
T3
,
0
1
IR4
T7
TS
T5
T4
T3
1
0
0
IR3
T7
T6
T5
T4
T3
0
1 1
IR2
T7
TS
T5
T4
T3
0
1
0
lA'
T7
TS
T5
T4
T3
0
0
,
IRO
T7
TS
T5 T4
T3
0 0 0
'
.....
10.
IntInupt
V.tor
.,..
...
es
.,.rll
....
3.2 INTERRUPT PRIORITIES
A variety
of
modes and commands are available for con-
trolling
interrupt priorities
of
the 8259A. All
of
them are
programmable, that is, they may be changed dynamic·
ally under software control.
With
these modes and com·
mands, many
possibilities
are conceivable, giving the
user enough versatility for almost any interrupt con·
trolled application.
Fully Ne.ted Mode
PRIORIlY
I,
0 7
65"
32'1
c
Fitlure 11. A-C.
Some
VariaIlona
01
Priorily
Slrucll""
In
Ille
Fully
Nelled
lIode
Further explanation
of
the fully nested mode, in this
section,
is
linked with information
of
general 8259A in-
terrupt operations. This
is
done
to
ease explanation
to
the user in both areas.
In general, when an interrupt is acknowledged, the
highest
priority
request is determined from the
IRR
(In·
terrupt Request Register). The interrupt vector
is
then
placed on the data bus. In addition, the corresponding
bit in the
ISR
(In·Service Register)
is
set to designate the
41
routine in service. This
ISR
bit
remains set until
an
EOI
(End·Of·lnterrupt) command is issued
to
the 8259A.
EOI's will be explained in greater detail shortly.
In the fully nested mode, while an
ISR
bit is set. all fur-
ther requests
of
the same or lower priority are inhibited
from generating an interrupt
to
the microprocessor. A
higher priority request, though. can generate
an
inter-
rupt, thus vectoring program execution to
its
service
routine. Interrupts are only acknowledged, however,
if
the microprocessor has previously executed
an
"Enable
Interrupts"
instruction. This is because the interrupt
request pin on the microprocessor gets disabled auto-
matically after acknowledgement of any interrupt. The
assembly language instructions used to enable inter·
rupts are
"EI"
for 808OA/8085A and
"STI"
for 8086/8088.
Interrupts can be disabled by using the instruction
"01"
for
8OBOA/
8085A and
"eLi"
for 8086/8088. When a
routine is completed a
"return"
instruction is executed,
"RET" for
BOBOA/B085A
and "IRET" for 8086/8088.
Figure
12
illustrates the correct usage of interrupt
related instructions and the interaction
of
interrupt
levels in the fully nested mode.
Assuming the
IR
priority assignment for the example in
Figure
12
is
IRO
the highest through
IR7
the lowest. the
sequence is as follows. During the main program, IR3
makes a request. Since interrupts are enabled, the
l"I"Ili"r"",,,,,,r,,,,,,,e,lI!!'lI!!',,,,r
ieo
U,a,,..tI"loFlIl:lItol"l
tl"\
tho.
IQ":I
C!!,c,rui,..o
rl"lllltiJ"\o
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