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INTERRUPT AEQueSTS
Figure 18. C
..
"decl82SI"'S
22 Inlerrupt L.enis
sequence
of
events
that
occur
during a valid
interrupt
request from a slave. Suppose a slave IR
input
has
received an
interrupt
request. Assuming
this
request
is
higher
priority
than
other
requests and in·service levels
on the slave, the slave's INT pin is driven high. This
signals
the
master
of
the request by causing
an
inter-
rupt
request
on
a designated IR
pin
of
the
master, Again,
assuming
that
this
request
to
the
master
is
higher priori-
ty
than
other
master requests and in-service levels
(possibly
from
other
slaves), the
master's
INT pin
is
pulled
high,
interrupting
the processor.
The
interrupt
acknowledge sequence appears
to
the
processor
the same as the non·cascaSiing
interrupt
acknowledge sequence; however,
it's
different
among
the 8259A's. The
first
INTA
pulse
is
used by all the
8259A's
for
internal set-up purposes and,
if
in the
8080/8085 mode,
the
master
will
place the CALL opcode
on the
data
bus. The
first
INTA
pulse
also
signals
the
master
to
place the requesting slave's
10
code on the
CAS lines. This
turns
control over
to
the slave for the
rest
of
the
interrupt
acknowledge sequence, placing the
appropriate pre-programmed
interrupt
vector on the
data bus,
completing
the interrupt request.
During the
interrupt
acknowledge sequence, the cor-
responding ISR
bit
of
both
the master and the slave get
set. This means
two
EOI
commands
must
be issued
(if
not in the
automatlc
EOI
model, one for the master and
one for the slave.
Special consideration should
be taken when mixed
interrupt requests are assigned
to
a master 8259A; that
is, when some
01
the master's IR
inputs
are used
lor
slave
interrupt
requests and some are used
for
individ-
ual
interrupt
requests.
!n
this
type
of
structure, the
master's
IRO
must
not be used for a slave. This is
because when an IR
input
that
isn't
initialized
as
a slave
receives
an
interrupt request, the CASO-2Iines
won't
be
activated,
thus
staying in the
default
condition
address-
ing for
I~O
(slave
IRQ).
If
a slave
is
connected
to
the
master's
IRO
when a non-slave interrupt occurs on
another master
IR
input, erroneous
conditions
may
48
result. Thus
IRO
should be the last
choice
when assign-
ing slaves
to
IR inputs.
Special
Fully
Nested Mode
Depending on the application, changes in the nested
structure
of the cascade mode may be desired. This
IS
because the nested
structure
01
a slave 8259A differs
from that
of
the normal full}7 nested mode. In the cas·
cade mode,
if
a slave receives a higher priority interrupt
request than one which
is
in service (through the same
slave),
it
won't
be recognized by the master. This is
because the master's ISR
bit
is
set, ignoring all requests
of
equal or lower priority.
ThUS,
in this case, the higher
priority slave interrupt
won't
be serviced until after the
master's ISR
bit
is reset by
an
EOI
command. This is
most
likely after the completion
01
the lower priority
routine.
If
the user wishes to have a truly fully nested structure
within
a slave
B~59A,
the special
fully
nested mode
should be used. The speCial fully nested mode
IS
pro·
grammed in the master only. ThiS is done
during
the
master's· initialization. In thiS mode the master will
ignore only those interrupt requests
01
lower priority
than the set
ISR
bit
and
will
respond to all requests of
equal or higher priority. Thus II a slave
receives a higher
priority
request than one in service,
it
Will be recognized
To
insure proper Interrupt operation when
USing
the
special fUlly nested mode. the software must
determine
if
any other slave interrupts are
still
in service before
issuing
an
EOI
command to the master. This
IS
done
by
resetting the appropriate slave ISA
bit
With
an
EOI and
then reading
its
ISR
II
the ISR contains all zeros. there
aren't any
other
interrupts
Irom
the slave 'n service and
an
EOI
command can be sent to the
master
If.
the ISR
isn't
all zeros,
an
EOI command
shouldn't
be sent to the
master. Clearing the master's
ISR
bit
with
an
EOI
com·
mand
while
there are
still
slave interrupts In service
would
allow
lower priority Interrupts to be recognized at
the
master. An example
of
thiS process is shown
In
the
second
application
in the
"Applications
Examples" sec·
tion.
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