LG GW520 - Page 55

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LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
4. RF Circuit Technical Brief
GW520 service manual
[Figure 4.1-2] RF Functional Block Diagram
I/IX
Q/QX
FSYSIN_PM
RX1/RX1X 850MHz
RX2/RX2X 900MHz
RX3/RX3X 1800MHz
RX4/RX4X 1900MHz
TX1 850/900MHz
TX2 1800/1900MHz
VBIAS
FSYSOUT1
EN_PM
DATA _PM
CLK_PM
FSYSOUT2
FSYSOUT3
VCO_RC
2.7...2.95V Suppl y1.4...1.6V Suppl y
fast
PFD
Integrated
3.8GHz V CO
Sigma-Delta
MASH Modulator
multi modulus divider
26 MHz
VCO
control
fast
CP
3W bus
sequencing
NI.NF
MOD
÷
4
÷2
OLG
adjus t
Timing
&
Measur e
ment
on chi p
loop fi lter
cordic
I/Q
=>
R/φ
d/dt
Q
÷
4
÷2
VCO-LDO
Bias DAC
2
2
2
2
PGA
6dB
PGA
1dB
.125dBRamp
SMARTi PM
DAC
Dig
PGA
I
ADC
ADC
Bias
TXOUTH/TX OUTHX
1920-1980 MHz
(band I)
RXINH/RXINHX
2110-2170 MHz ( band I)
RXINM/RXINMX
1930-1990 MHz (band II/III)
TXOUTL/TXOUTLX
824-915 MHz
(band V/V I/VIII)
TXOUTM/TXOUTMX
1850-1910 MHz
(band II/III)
RX INL/RX INLX
869-960 ( band V/VI/V III)
RXBAND1
RXBAND2
RXBAND3
EN / DATA / CLK
FSYSIN_3G
RXQ/RXQX
RXI/RX IX
ENPGC
DATAPGC
CLKPGC
TXI/TXIX
TXQ/TXQX
TXGC
MAS TE RO N
LD
TXHSMODE
TXEN
TXBAND1
TXBAND2
TXBAND3
1.71...2.95V S upply
:2
0
o
90
o
VCO
Frac-PLL
LF
:4
0
o
90
o
I
Q
0
o
90
o
VCO
Frac-PLL
LF
0
o
90
o
Internal
1.5V
LDO
TX gain
control
3-wire bus
RX PGC
FSYS
SMARTi 3G
:4
:2
3-wire bus
:2
0
o
90
o
2.7...2.95V S upply
1.5V S uppl y