LG GX500 - 7 Circuit Diagram

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7. CIRCUIT DIAGRAM
LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
1V8_SD
101R
0033
101CU1.0
0.1U
C102
0.1U
C103
2V62_VIO
1V8_SD
VBAT
K22
201R
0.1U
C104
501CU1.0
601CU1.0
3
01
R
K0
3
3
C107
0.1U
801CU1.0
901CU1.0
V_BUS
0.1U
C110
111CU1.0
22R104
501R
K01
K5.1601R
211CU1.0
C113
0.1U
22R107
411CU10.0
801R
K01
2V62_VIO
VBAT
511CU1.0
TP102
C116
0.1U
TP103
0.1U
C117
0.1U
C118
TP104
7.5pF
FL102
01 5
64
73
82
91
INOUT_A1 INOUT_B1
INOUT_A2 INOUT_B2
INOUT_A3 INOUT_B3
INOUT_A4 INOUT_B4
1G 2G
911CU1.0
0.1U
C120
U1 121C
221CU1.0
K
001
01
1
R
321CU
1
421CU10.0
C125
0.1U0.1U
C126
2V62_VIO
K09
3
1
11
R
2V62_VIO
C127
0.1U
2V9_SIM
2V11_RTC
TP105
K00
1
901R
R113 100K
2V5_VAUDA
2V5_VAUDB
821CU1
TP106
U1 921C
031CU1.0
K5.1411R
7.5pF
FL101
01 5
64
73
82
91
INOUT_A1 INOUT_B1
INOUT_A2 INOUT_B2
INOUT_A3 INOUT_B3
INOUT_A4 INOUT_B4
1
G
2
G
1V8_SD
X101
32.768KHz
2 1
TP107
1V8_SD
131CU1.0
2V62_VIO
UT101
12
11
10
9
8
7
6
5
4
3
2
1
GND
RX
TX
NC1
ON_SW
VBAT
NC2
NC3
NC4
DSR
RTS
CTS
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
3G 2.5G
231CU1.0
2V62_VIO
1511R
TP108
TP109
0.1U
C133
K01611R
431CU1.0
0.1U
C135
C136
0.1U
HN001101L
HN001201L
731C
N022
C138
0.1U
R117
100K
HN001301L
2V62_VIO
TP110
1V35_VPLL
HN001401L
C139
22N
22P
C140
811R
K
1
141CU1.0
TP111
241CU1
0.1U
C143
1V8_SD
C144
22P
22N
C145
641CU1.0
K001911R
02
1
R
K1
1V35_CORE
TP112
741C
P51
841CU1.0
P51
941C
L
K
J
I
H
G
F
E
D
C
B
A
12
11
10
9
8 7 6 5 4 3 2 1
L
K
J
I
H
G
F
E
D
C
B
A
12
11
10
9
8 7 6 5 4 3 2 1
U101
6E 1K 4H 4E 2E 3E 41F 61G 61J 91H 4F 1E 3F 5
F
51F 91C 31Y 71A 41C 71G 91F 91E 81F 51G 91G 91B 71E 81E 91D 61E 61U 51T 61L 81L 91L 91M 71L 71M 81M 91P 91N 91V 81V 91U 81U 91T 81T 91
R
81R 81P 71P 5G 1F 3G 4G 3K 1J 2J 5H 3H 5J 1G 01A 6A 6B 4A 9E 7B 8E 8A 9B 8B 8C 9A 11A 9F 7C 8
F
1D 4
C
1B 3
C
5C 5E 1C 2
C
4B 3B 2A 3A 7E 5B 6C 7F
Y8
G18T10
H17Y9
J19U11
J18AA7
C10
R15B16
R16E14
Y14
H18F16
W14F13
AA15C16
AA16C15
B18
U10A18
W8
Y7G2
F2
Y4
U5W11
V3F6
AA2D2
Y2D3
Y3A14
W3F10
C9
R3B11
L1A12
M1E10
K2
K17
T11K18
H16
T5
T6H15
U4U12
U3W12
N4C18
N3
P3B17
R2E15
D18
P4D17
M4
M5
R1
L4
K5
K4
J4
N2C13
P2B15
N1B12
M3C12
L5E12
J3C11
L3B13
M2F12
E11
T4A15
T3F11
P5B14
T2E13
R4
T1K15
R5M16
W2M15
U2N15
N5M12
V1K16
W9
U9U15
Y6Y16
W7AA17
T9W16
W6Y17
AA5AA18
Y5W17
U7Y18
T7Y19
AA4V17
W5W18
U6
T8
W4
U8
21Y
11Y
51Y
9AA
11AA
21AA
01Y
8AA
71N
81N
71U
91W
71R
71T
51J
61N
61P
41U
31T
51W
31U
41T 61T
51L
51P
2L
21T
31W
41AA
31AA
91K 31A 01B
1H
71J
2H
7A 2B
71C
61A
5A
71F
01W
1W
2V
1U
1P
1Y
6AA 3AA
01AA
8M
9M
01M
11M
8K 9K
01K
11K 21K
9N
01N
8L
9L
01L
11L
21L
9J
01J 11J
11
N
91AA
1AA
91A
1A
1A_RENROC
2A
_
RE
N
R
O
C
1AA_RENROC
2AA_RENROC
C
N
1
NIAM_
D
DV
2
NIAM_
D
DV
3
N
IAM
_
D
DV
4
N
IAM
_
D
DV
5
NIAM_
D
DV
6NIAM_DDV 7NIAM_DDV 8NIAM_DDV
9NIAM_DDV 01NIAM_DDV 1NIAM_SSV 2NIAM_SSV
3NIAM_SSV 4NIAM_SSV 5NIAM_SSV 6NIAM_SSV 7NIAM_SSV 8NIAM_SSV
9NIAM_SSV 1MTE_MEM_PDDV
2MTE_MEM_PDDV 3MTE_MEM_PDDV
4MTE_MEM_PDDV 5MTE_MEM_PDDV 1MTE_MEM_PSSV 2MTE_MEM_PSSV 3MTE_MEM_PSSV 4MTE_MEM_PSSV
AGID_PDDV BGID_PDDV
1CGID_PDDV 2CGID_PDDV
DGID_PDDV
2GID_PSSV
1GID_PSSV 3GID_PSSV
EGID_PDDV
4GID_PSSV
CMM_PDDV
MIS_PDDV
CTR_DDV CTR_SSV
LLP_DDV
LLP_SSV
SF_ESUF_DDV
BB_ADDV BB_ASSV
D
_A
D
DV
D_ASSV
M_ADDV M_ASSV
GB_ADDV GB_ASSV
NFERV
DNGA DRAUG
1RBV_A
D
DV
1RBV_ASSV 2RBV_ADDV
2
RBV_ASSV
TBV_ADDV TBV_ASSV
0TKPECART
1TKPECART 2TKPECART 3TKPECART
4TKPECART
5TKPECART 6TKPECART 7TKPECART
MEM_A0
MEM_A1
MEM_A2
MEM_A3
M_0 MEM_A4
M_1 MEM_A5
M_2 MEM_A6
M_3 MEM_A7
M_4 MEM_A8
M_5 MEM_A9
M_6 MEM_A10
M_7 MEM_A11
M_8 MEM_A12
M_9 MEM_A13
M_10 MEM_A14
MEM_A15
PAOUT11 MEM_A16
PAOUT12 MEM_A17
BB_I MEM_A18
BB_IX MEM_A19
BB_Q MEM_A20
BB_QX MEM_A21
MEM_A22
T_OUT0 MEM_A23
T_OUT1 MEM_A24
T_OUT2 MEM_A25
T_OUT3 MEM_A26
T_OUT4
T_OUT5 MEM_AD0
T_OUT6 MEM_AD1
T_OUT7 MEM_AD2
T_OUT8 MEM_AD3
T_OUT9 MEM_AD4
T_OUT10 MEM_AD5
T_IN0 MEM_AD6
T_IN1 MEM_AD7
MEM_AD8
MEM_AD9
MEM_AD10
MEM_AD11
MEM_AD12
MEM_AD13
MEM_AD14
RF_STR0 MEM_AD15
RF_STR1
RF_DATA MEM_CS0_N
RF_CLK MEM_CS1_N
MEM_CS2_N
AFC MEM_CS3_N
CLKOUT0 MEM_CSA0_N
F26M MEM_CSA1_N
SWIF_TXRX MEM_CSA2_N
MEM_CSA3_N
CC_IO
CC_CLK FCDP_RBN
CC_RST
MEM_WAITN
MMCI1_CMD MEM_ADVN
MMCI1_CLK MEM_RDN
MMCI1_DAT0 MEM_WRN
MMCI1_DAT1
MMCI1_DAT2 MEM_BFCLKO1
MMCI1_DAT3 MEM_BFCLKO2
MMCI2_CMD MEM_SDCLKO
MMCI2_DAT0 MEM_BC0_N
MMCI2_CLK MEM_BC1_N
FWP MEM_BC2_N
MEM_BC3_N
IRDA_TX
IRDA_RX MEM_RAS_N
MEM_CAS_N
TDO MEM_CKE
TDI
TMS F32K
TCK OSC32K
TRST_N RESET_N
RTCK RSTOUT_N
RTC_OUT
TRIG_IN VREFP
MON1 IREF
MON2
TRACESYNC SPCU_RQ_IN0
TRACECLK SPCU_RQ_IN1
PIPESTAT2 SPCU_RC_OUT0
PIPESTAT1 SPCU_RQ_IN2
PIPESTAT0
0
D_F
I
D
1D
_
FID
2D
_
FID
3
D_F
I
D
4
D_F
I
D
5D_FID 6D
_
FI
D
7D
_
FI
D
8D_FID
1S
C_FID
2S
C_F
I
D
DC
_
FID
RW_FID
D
R_FID
DH
_
FI
D
DV
_
FID
1TESER_FID 2
TESE
R_FID
0D
_
FIC
1
D_F
I
C
2
D_F
I
C
3D
_
FI
C
4D
_
FI
C
5
D_F
I
C
6D_FIC 7D_FIC
KLCP_FIC
CNYSH_FIC
CNYSV_FIC
2TUOKLC
DP_FIC
TESER_FIC
0NI_PK 1NI_PK 2NI_PK 3NI_PK 4NI_PK 5NI_PK 6NI_PK
0TUO_PK
1TUO_PK 2TUO_PK
3TUO_PK
11NPE 21NPE
11PPE 21PPE
11APPE 21APPE
1FERPE 2FERPE
12APPE 22APPE
1NCIM
1PCIM
2NCIM
2PCIM
1NXUA
1PXUA
2NXUA
2PXUA
DNGXUA
PCIMV NCIMV
0KLC_1S2I 1KLC_1S2I
X
R
_1S
2
I
XT_1S2I
0AW_1S2I
0KLC_2S2I 1KLC_2S2I
XR_2S
2
I
XT_2S2I
0AW_2S2I 1AW_2S
2
I
LCS_1C2I ADS
_
1C
2
I
TNI_MP
LCS_2C2I ADS_2C2I
TSRM_DXR_1FISU
RSTM_DXT_1FISU
N_STR_1FISU
N_STC_1FISU
TSRM_DXR_2FISU
RSTM_DXT_2FISU
N_STR_2FISU N_STC_2FISU
TSRM_DXR_3FISU
RSTM_DXT_3FISU
KLCS_3FISU
0NIPSD 1NIPSD
1TUOPSD
K5
7
2
11
R
H8ACS0SJ0BCR-46M
U102
01P 1P 4M 3M 5G 1G 3F 5E 01B 2B 1B 8H 7H 7J
R10G10
R9F9
R2E10
R1D9
A10C10
A9N10
A2M9
L10
E7K10
F8J9
G6
J8G9
H2F10
G2E9
K1D10
E3C9
G8N9
J2M10
L9
C7K9
C8J10
D7
D8M2
D6P9
E8J1
D5H9
F6C1
F7B9
E6
H4M1
H3P8
F5H10
E4H1
F4D1
G4B8
G3
J4P6
H5C5
H6
J5N5
J6B5
G7
K6C6
K5C3
K7C4
L8B4
K8B7
L7B3
L6B6
L5
L4N8
M7
K2N7
J3P5
F1P4
F2N4
K3P3
D4P2
E2M8
D3N6
E1M6
D2P7
C2M5
L3N3
L2N2
L1N1
K4
A0
IO0 A1
IO1 A2
IO2 A3
IO3 A4
IO4 A5
IO5 A6
IO6 A7
IO7 A8
IO8 A9
IO9 A10
IO10 A11
IO11 A12
IO12 BA0
IO13 BA1
IO14
IO15 DQ0
DQ1
_CE DQ2
_RE DQ3
_WEN DQ4
CLE DQ5
ALE DQ6
_WP DQ7
R_B DQ8
DQ9
VCCN0 DQ10
VCCN1 DQ11
DQ12
VSSN0 DQ13
VSSN1 DQ14
DQ15
VDD0 DQ16
VDD1 DQ17
VDD2 DQ18
VDD3 DQ19
VDD4 DQ20
VDD5 DQ21
DQ22
VSS0 DQ23
VSS1 DQ24
VSS2 DQ25
VSS3 DQ26
VSS4 DQ27
VSS5 DQ28
DQ29
VDDQ0 DQ30
VDDQ1 DQ31
VDDQ2
VDDQ3 _CS
VDDQ4 CK
VDDQ5 CKE
VDDQ6 _WED
VDDQ7 _RAS
VDDQ8 _CAS
VDDQ9 DQM0
DQM1
VSSQ0 DQM2
VSSQ1 DQM3
VSSQ2
VSSQ3 DNU0
VSSQ4 DNU1
VSSQ5 DNU2
VSSQ6 DNU3
VSSQ7 DNU4
VSSQ8 DNU5
VSSQ9 DNU6
1CN 2CN 3CN 4CN 5CN 6CN 7CN 8CN 9CN
01CN 11CN 21CN 31CN
41CN
LRTC_ECRUOSER
_RAS_S1
_RAS_S1
I
IX
Q
QX
PV_TA
D_BS
U
XT_TRAU_1MIS
S1_ADD[0]
S1_ADD[0]
S1_ADD[1]
S1_ADD[1]
S1_ADD[10]
S1_ADD[10]
S1_ADD[5]
S1_ADD[5]
S1_ADD[11]
S1_ADD[11]
S1_ADD[6]
S1_ADD[6]
S1_ADD[12]
S1_ADD[12]
S1_ADD[7]
S1_ADD[7]
S1_ADD[13]
S1_ADD[13]
S1_ADD[8]
S1_ADD[8]
S1_ADD[14]
S1_ADD[14]
S1_ADD[9]
S1_ADD[9]
S1_ADD[15]
S1_ADD[15]
S1_ADD[16]
S1_ADD[16]
S1_ADD[16]
S1_ADD[17]
S1_ADD[17]
S1_ADD[17]
S1_ADD[18]
S1_ADD[18]
S1_ADD[19]
S1_ADD[19]
S1_ADD[2]
S1_ADD[2]
S1_ADD[20]
S1_ADD[20]
S1_ADD[21]
S1_ADD[21]
S1_ADD[22]
S1_ADD[22]
S1_ADD[23]
S1_ADD[23]
S1_ADD[24]
S1_ADD[24]
S1_ADD[3]
S1_ADD[3]
S1_ADD[4]
S1_ADD[4]
S1_DATA[0]
S1_DATA[0]
S1_DATA[0]
S1_DATA[1]
S1_DATA[1]
S1_DATA[1]
S1_DATA[3]
S1_DATA[3]
S1_DATA[3]
S1_DATA[4]
S1_DATA[4]
S1_DATA[4]
S1_DATA[5]
S1_DATA[5]
S1_DATA[5]
S1_DATA[6]
S1_DATA[6]
S1_DATA[6]
S1_DATA[7]
S1_DATA[7]
S1_DATA[7]
S1_DATA[2]
S1_DATA[2]
S1_DATA[2]
S1_ADD[25]
S1_ADD[25]
_NAND_CS_S1
_NAND_CS_S1
_BC0_S1
_BC0_S1
_BC1_S1
_BC1_S1
S1_FCDP
S1_FCDP
_CAS_S1
_CAS_S1
S1_CKE
S1_CKE
_RAM_CS_S1
_RAM_CS_S1
_DPRAM_CS_S1
_RD_S1
_RD_S1
_WR_S1
_WR_S1
_WR_S1
UART_SEL
BAT_ID
S1_RF_TEMP
N_CIM_1MIS
N_CIMSH_1MIS
P_CIM_1MIS
P_CIMSH_1MIS
TNI_MP
_RESET
RTC_OUT
TXON_PA
S1_PA_BAND
PA_MODE
XR_TRAU_1MIS
NE_OXCV
VREFN
NFERV
TNI_3GS
USB_OEN
DI
_
DCL
KEY_ROW1
GODW
S1_SDCLKI
S1_SDCLKI
MV_0ES_BSU
LCS_2C2I
S1_ADD[26]
S1_ADD[26]
S1_ADD[27]
S1_ADD[27]
S1_ADD[28]
S1_ADD[28]
S1_ADD[29]
S1_ADD[29]
S1_ADD[30]
S1_ADD[30]
_BC2_S1
_BC2_S1
_BC3_S1
_BC3_S1
PA_LEVEL
S1_DATA[8]
S1_DATA[8]
S1_DATA[8]
S1_DATA[9]
S1_DATA[9]
S1_DATA[9]
S1_DATA[11]
S1_DATA[11]
S1_DATA[11]
S1_DATA[12]
S1_DATA[12]
S1_DATA[12]
S1_DATA[13]
S1_DATA[13]
S1_DATA[13]
S1_DATA[14]
S1_DATA[14]
S1_DATA[14]
S1_DATA[15]
S1_DATA[15]
S1_DATA[15]
S1_DATA[10]
S1_DATA[10]
S1_DATA[10]
KEY_ROW0
0
D_FID
1
D_FID
2D
_
FID
3
D_FI
D
4
D_FID
5
D_FID
6D
_
F
I
D
7
D_FI
D
S
C_FID
D
R_FID
RW_FI
D
S1_SDCLKO
S1_SDCLKO
KEY_COL3
KEY_COL0
KEY_COL1
KEY_COL2
SGR_INT
COE_ RPP_ NO_RWP_RGS
_DPRAM_SEM_S1
NE_SAIB
_
CIM
LES_2MIS_1MIS
L
RTC_LB_D
C
L
TED_CMM
ADS_2C2I
MMC_CMD
MMC_CLK
MMC_D0
RPWRON_EN
UART_RX
SIM1_DSR
SIM1_DSR
UART_TX
USB_DM
USB_DP
_DPRAM_INT_S1
_DPRAM_BUSY_S1
SG3_SIM1_RST
SG3_SIM1_CLK
SG3_SIM1_IO
26MHZ_MCLK
RF_DA
RF_CLK
RF_EN
SGR_RESETN
LES_BS
U
TNI_LECCA
TESER_FI
D
NORWPR
_CHG_EN
T
N
I_
WSU
N_VCR_1MIS
P_VCR_1MIS
L_KPS_SH_1MIS
R_KPS_SH_1MIS
DC_FID
LIN_MOTOR_EN
MWP_BIV
KLCM_FIC
CNYSV_FIC
KLCP_FIC
CNYSH_FIC
XT_TRAU_TB
XR_TRAU_TB
WLAN_SDIO[3]
BT_HOST_WAKEUP
K23KLC
WLAN_HOST_WAKEUP
LES_SH_MF
WLAN_CMD
WLAN_CLK
WLAN_SDIO[0]
WLAN_SDIO[1]
WLAN_SDIO[2]
PUEKAW_TB
WLAN_WAKEUP
LCS_1C2I
ADS_1C2I
DP_FIC
KLC_1S2I_1MIS
0AW_1S2I_1MIS
XT_1S2I_1MIS
XR_1S2I_1MIS
0D_FIC 1D
_
FIC
2
D_FIC
3
D_FIC
4D_FIC 5D
_
FIC
6D_FIC 7
D_FI
C
TESER_FIC
ELBANE_TB
WLAN_ENABLE
STR_TRAU_TB
STC_TRAU_TB
CNYSV_FID
LES_TB
TS_IRQ
NE_ODL_MAC
REG_ON
KEY_ROW4
NE_HCUO
T
BASE BAND PROCESSOR
ON BOARD ARM9 JTAG & ETM INTERFACE
UART
2G NAND(LB/128Mx16bit) +1G SDR SDRAM(8Mx4x32bit)
EUSY0347505, Hynix