LG GX500 - Page 126

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LGE Internal Use OnlyCopyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
C712
0.1u
VBAT
CN701
2
1
C702
0.1uF
10u
C701
C704
2.2uF
1uC705
1uC706
107L
Hu1.0
207L
Hu1.0
C708
0.1uF
C709
2.2uF
U701
LM49151TL
4E 4D 3D 4C 2A
E2B3
B2
A1
C3
E3
C2
D2C1
A3D1
A4E1
4B 1B
DDV DDVSL
INM+ LSOUT+
INM- LSOUT-
INL SET
INR
HPL
BYPASS
I2CVDD
SDA
SCL HPR
DNG
SSVPC
N1C P1C
DNGPC
K001
997R
27pF
C710C711
27pF
FB701
2V62_VIO
2.2u
C713
smhoK001
207R
C714
1U
C715
47pF
47pF
C716
C717
100pF
220nC703
220nC707
VA701
L703 47n
VA702
FSA2268TUMX_F113U703
94
63
52
71
810
1B0 1A
1B1 S1
2B0 2A
2B1 S2
GND VCC
L704 47n
OJ701
R703 47K
R704 47K
R705 47K
VSD2_1V8
OJ702
47KR706
OJ703
1V8_SD
1V8_SD
TP701 TP702
817C U1
R707 47K
U1917C
02
7
C U1
CYDM128B16-55BVXI
U702
J6
F6
E8E10
B8E6
F10E5
H7E1
J5C10
F5A10
E2A5
F1D1
H9E3
H8D2
C6F2
J4G1
D4E4
A6K5
D3F3
B7G5
B5H5
C5H4
A4K4
B6K6
D6G4
A3K3
D5J3
B4H3
A2K2
B3J2
C4K1
A1G3
B2H2
B1J1
C3G2
C2F4
C1H1
A7F9
C7G9
D7G10
A8G8
C8G7
A9H10
B9J10
D8J9
C9K10
B10J8
D9K9
E7J7
F7G6
D10K8
E9H6
F8K7
IO0L
IO0R
IO1L IO1R
IO2L IO2R
IO3L IO3R
IO4L IO4R
IO5L IO5R
IO6L IO6R
IO7L IO7R
IO8L IO8R
IO9L IO9R
IO10L IO10R
IO11L IO11R
IO12L IO12R
IO13L IO13R
IO14L IO14R
IO15L IO15R
A0L A0R
A1L A1R
A2L A2R
A3L A3R
A4L A4R
A5L A5R
A6L A6R
A7L A7R
A8L A8R
A9L A9R
A10L A10R
A11L A11R
A12L A12R
R__WL R__WR
_UBL _UBR
_LBL _LBR
_CEL _CER
_OEL _OER
_BUSYL _BUSYR
_SEML _SEMR
_INTL _INTR
0DR0 IRR0
0DR1 IRR1
0DR2 NC1
0DR3 NC2
0DR4 _SFEN
VSS1 M__S
VSS2 VCC1
VSS3 VCC2
VSS4 VDDIOL1
VSS5 VDDIOL2
VSS6 VDDIOR1
VSS7 VDDIOR2
VSS8
VSS9
47KR708
VSD2_1V8
47KR709
OJ705
47KR711
L
K
J
I
H
G
F
E
D
C
B
A
12
11
10
9
8 7 6 5 4 3 2 1
L
K
J
I
H
G
F
E
D
C
B
A
12
11
10
9
8 7 6 5 4 3 2 1
2V62_VIO
S1_ADD[0]
S1_ADD[1]
S1_ADD[10]
S1_ADD[5]
S1_ADD[11]
S1_ADD[6]
S1_ADD[12]
S1_ADD[7]
S1_ADD[8]
S1_ADD[9]
S1_ADD[2]
S1_ADD[3]
S1_ADD[4]
S1_DATA[0]
S1_DATA[1]
S1_DATA[3]
S1_DATA[4]
S1_DATA[5]
S1_DATA[6]
S1_DATA[7]
S1_DATA[2]
_BC0_S1
_BC1_S1
_DPRAM_CS_S1
_RD_S1
_WR_S1
S1_DATA[8]
S1_DATA[9]
S1_DATA[11]
S1_DATA[12]
S1_DATA[13]
S1_DATA[14]
S1_DATA[15]
S1_DATA[10]
_DPRAM_SEM_S1
_DPRAM_INT_S1
_DPRAM_BUSY_S1
SPK_N
SPK_N
SPK_P
SPK_P
RCV_N
RCV_P
S2_DATA[15]
S2_DATA[14]
S2_DATA[13]
S2_DATA[12]
S2_DATA[11]
S2_DATA[10]
S2_DATA[9]
S2_DATA[8]
S2_DATA[7]
S2_DATA[6]
S2_DATA[5]
S2_DATA[4]
S2_DATA[3]
S2_DATA[2]
S2_DATA[1]
S2_DATA[0]
_WR_S2
_RD_S2
_BC1_S2
_BC0_S2
_DPRAM_CS_S2
S2_ADD[9]
S2_ADD[8]
S2_ADD[7]
S2_ADD[6]
S2_ADD[5]
S2_ADD[4]
S2_ADD[3]
S2_ADD[2]
S2_ADD[12]
S2_ADD[11]
S2_ADD[10]
S2_ADD[1]
S2_ADD[0]
_DPRAM_BUSY_S2
_DPRAM_INT_S2
FM_L
FM_R
SIM1_HS_SPK_L
SIM1_HS_SPK_R
HSO_L
HSO_R
FM_HS_SEL
I2C1_SCL
I2C1_SDA
AMP_IN_L
AMP_IN_L
AMP_IN_R
AMP_IN_R
AUDIO AMP SUB SYSTEM
SPK
EUSY0285602, CYPRESS
128K DUAL PORT STATIC RAM
7. CIRCUIT DIAGRAM