LG GX500 - Page 19

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3. TECHNICAL BRIEF
GX500 Operational Description Revision A
LG Electronics 20/143 LGE Property
z Functional Hardware block
- CPU and DSP Timers
- MOVE coprocessor performing motion estimation for video encoding algorithms
(H.263, MPEG-4)
- Programmable PLL with additional phase shifters for system clock generation
- GSM Timer Module that off-loads the CPU from radio channel timing
- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)
- GMSK Modulator: gauss-filter with B*T=0.3
- EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter
- Hardware accelerators for equalizer and channel decoding.
- Incremental Redundancy memory for EDGE class 12 support
- A5/1, A5/2, A5/3 Cipher unit
- GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission
- Advanced static and dynamic power management features including TDMA-Frame
synchronous low power mode and enhanced CPU modes(idle and sleep modes)
- Pulse Number Modulation output for Automatic Frequency Correction(AFC)
- Serial RF Control interface: support of direct conversion RF
- A Universal Serial Interface(USIF) enabling asynchronous (UART) of synchronous (SPI)
serial data transmission
- 3 USIF with autobaud detection, hardware flow control and integrated
- A dedicated Fas IfDA Controller supporting IrDA’s SIR,MIR and FIR standards
(up to 4Mbps)
- I2C-bus interface (e.g. connection to S/M power)
- A fast display interface supporting serial and parallel interconnection
- An ITU-R BT.656 compatible Camera interface.
- Programmable clock output for a camera
- An multimedia/Secure Digital Card Interface (MMCI/SD:SDIO capable)
3.2.1.3 External Devices connected to memory interface
Table 3-1. Memory interface
Device Name Maker Remark
NAND FLASH H8ACS0SJ0MCP-56M Hynix
SDR H8ACS0SJ0MCP-56M Hynix
LCD
DPRAM