Marantz 112 - Page 5

The
DC
voltage
obtained
by
rectifing
the
sub
IF
output
signal
from
the
H2065
is
applied
to
the
base
of
H206
and
turns
on
it,
if
the
sub
IF
output
is
greater
than
predetermined
level
(muting
threshold
level).
When
the
H206
is
turned
on,
the
H207
is
turned
off,
allowing
the
emitter-collector
resistance
to
be
increased
and
the
collector
voltage
to
be
raised
to
about
9V.
The
raised
collector
voltage
increases
the
gate
bias
voltage
and
turns
on
the
switching
FET
H212,
decreasing
the
sourcedrain
resistance
to
near
zero
ohm
and
allowing
the
audio
signal
applied
to
the
source
to
flow
to
the
decoding
IC
pin
@)
through
the
source-drain
path.
When
the
input
signal
is
lower
than
predetermined
level,
the
DC
output
obtained
is
small
and
can
not
turn
on
the
H206,
thus
H206
keeps
its
turn-off
state.
This
makes
H207
turn
on,
decreasing
the
collector
voltage
and
turning
H212
off.
Thus
no
audio
signals
can
pass
through
the
FET.
The
transistor
H208
also
turns
off
when
the
transistor
H20/7
turns
on,
and
makes
the
transistor
H213
turn
on,
which
is
connected
to
pin
on
the
MPX
decoding
IC.
Therefore,
pin
is
equivalently
grounded,
and
the
operation
of
the
IC
becomes
monaural.
This
prevents
misoperation
of
stereo
due
to
undesirable
noises
during
deviation
of
tuning.
3.2
MPX
Stereo
Decoding
Circuit
The
stereo
composite
signal
from
the
FM
Detector
undergoes
phase
compensation
by
R289
amd
C255,
is
led
through
the
muting
switching
FET
H212
to
the
input
terminal
pin
(2)
of
the
MPX
stereo
decoding
1C
H215
on
PLL
(Phase
Locked
Loop)
basis,
and
is
decoded
into
the
left
and
right
stereo
signals,
which
become
available
at
pins
@)
and
©
respectively.
These
decoded
left
and
right
stereo
audio
signals
are
introduced
through
the
low
pass
filter
consisting
of
L207
to
1210
and
C273
to
C282
for
elimination
of
undesirable
residual
switching
signal
and
through
the
de-emphasis
network
consisting
of
R308,
R309,
C283
and
C284,
into
the
npn-pnp
direct
coupled
audio
amplifier,
where
the
signals
are
amplified
to
a
required
level
for
the
output
from
J226
and
J227.
From
these
jacks,
the
audio
signals
are
led
through
the
function
switch
and
FM
Dolby
level
preset
resistors
RSO3
and
RSO4
to
the
output
terminals
on
the
rear
panel.
Figure
2
presents
an
internal
block
diagram
showing
the
functions
of
the
PLL
basis
MPX
stereo
decoding
IC
HA1156.
STEREO
LPF
76KHz
38KHz
COMPOSITE
|
SIGNAL
AUDIO
19KHz
|
PHASE
DC
+2
INPUT
AMPLIFIER
a
\
AMPLIFIER
veo
(DIV-1)
STEREO
INDICATOR
LAMP STEREO
SWITCH
PHASE
O
29
DETECTOR
TRIGGER
(DIV-3)
(PD-2)
O
19KHz
STEREO COMPOSITE
SIGNAL
38KHz
SQUARE
WAVE
DECODER
LO OR
AUDIO OUTPUT
+2
(DIV-2)
38KHz
Figure 2. Block Diagram of the HA1156
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