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© 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 14
l 40 stage barrel shifter (up to 16 bits left or right)
l Shift accumulators, W registers or memory
l Accumulator rounding during store operation
l Conventional rounding
l Convergent (unbiased) rounding
l Modulo addressing (for filters): both AGU’s
l Bit reversed addressing (for FFT): one AGU
l Zero Overhead Instruction Loop Support
l REPEAT: Repeat next instruction N times
l DO: Repeat loop N times
l Constant or variable loop count
DSP Features
But that’s not all! The dsPIC30F provides more features to ensure
efficient DSP algorithm performance.
It contains a 40-bit barrel shifter, which can shift data in the
accumulator, W register or RAM up to 16-bits left or right, in a single
instruction cycle. This is of immense utility, for example, while
normalizing arrays of signal samples, or for unpacking data from bit-
streams received over a communication channel.
The data in an accumulator may be rounded before being stored. The
dsPIC30F CPU supports 2 different ways of rounding, known as
Conventional Rounding and Convergent Rounding.
To support digital filtering, hardware support for circular buffers is
provided through a special addressing mechanism known as Modulo
Addressing. This feature eliminates the software overhead involved in
boundary checking in circular buffers, such as those used in digital
filtering algorithms for accessing data samples from delay lines.
For efficient implementation of Fast Fourier Transform or FFT
operations, a Bit Reversed Addressing mode is provided to speed up
the re-ordering of data.
Finally, in-built hardware support is provided to support zero overhead
program loop control. This is accomplished through special DO and
REPEAT instructions that eliminate the software overhead associated
with loop management. For example, an entire array of data can be
copied into another array using only two instruction words!
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