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© 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 15
dsPIC30F CPU Block Diagram
W Array
16 x 16
23-bit PC
Control
DSP
Engine
MCU
ALU
Data Memory
(RAM)
32K x 16 bit
DSP: dual access
MCU: single access
X AGU
Y AGU
Instruction
Pre-fetch & Decode
Program
Memory Data
Access Control
Address Path
MCU/DSP Data Path
Program Data/Control Path
DSP Data Path
Program
Memory
4M x 24 bit
Linear
This high level block diagram depicts the core elements of the
dsPIC30F architecture. Notice the distinct Program Memory and Data
Memory blocks, consistent with a Harvard Architecture. However, by
using the Table instructions or PSV, constant data coefficients may be
stored and accessed from Program Memory. This is very useful for
executing digital filters in RAM-intensive applications.
Another important element to observe in this diagram in the presence of
two Address Generation Units, or AGUs. As mentioned in the context of
MAC operations, this allows accessing two data operands during a
single instruction cycle, for instance: a coefficient and a data sample in
a filtering operation.
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