2006-2019 Microchip Technology Inc. DS30009711C-page 15
I/O Ports with PPS
4.4 Controlling Configuration Changes
Because peripheral remapping can be changed during run time, some restrictions on peripheral
remapping are needed to prevent accidental configuration changes. dsPIC33/PIC24 devices
include three features to prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
4.4.1 CONTROL REGISTER LOCK
Under normal operation, writes to the RPINRx and RPORy registers are not allowed; attempted
writes will appear to execute normally, but the contents of the registers will remain unchanged.
To change these registers, they must be unlocked in hardware. The register lock is controlled by
the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing
IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence must be executed:
1. Write 46h to OSCCON<7:0>.
2. Write 57h to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
The unlock/lock sequence must be executed as an assembly language routine in the same man-
ner as changes to the oscillator configuration, because the unlock sequence is timing critical. If
the bulk of the application is written in C, or another high-level language, the unlock sequence
should be performed by writing inline assembly or using built-in functions provided by the
MPLAB
®
C30 C Compiler.
IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be
configured with a single unlock sequence, followed by an update to all control registers, then
locked with a second lock sequence.
4.4.2 CONTINUOUS STATE MONITORING
In addition to being protected from direct writes, the contents of the RPINRx and RPORy
registers are constantly monitored in hardware by shadow registers. If an unexpected change in
any of the registers occurs (such as cell disturbances caused by ESD or other external events),
a Configuration Mismatch Reset (CMR) will be triggered.
4.4.3 CONFIGURATION BIT PIN SELECT LOCK
As an additional level of safety, the device can be configured to prevent more than one write
session to the RPINRx and RPORy registers. The IOL1WAY (FOSC<IOL1WAY>) Configuration
bit blocks the IOLOCK bit from being cleared after it has been set once.
In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session.
Programming IOL1WAY allows users unlimited access (with the proper use of the unlock
sequence) to the Peripheral Pin Select registers.
Note: MPLAB
®
C Compiler provides built-in C language functions for unlocking the
_OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See the “MPLAB
®
C Compiler for PIC24 MCUs and dsPIC
®
DSCs
User’s Guide”
(www.microchip.com/DS51284) for more information.
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