DIGITAL PROPORTIONAL R/CSYSTEM
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2.4GHz
FHSS
SBUS signal:
High level 3.3V,100k baud rate, 8 data bits (9 bits to be selected in stm32), even parity (EVEN), 2 stop bits,
starting at 0x0F and ending at 0x00, 25 bytes in total, one frame of data every 14ms;
[0x0F] [data0] [data1] [data2] [data3] ... [data10] [flag] [0x00];arranged as follows:
Corresponding to 16 channels (ch1-ch16), each channel 11bit, channel data value range data1.... .data22:
is 200-1800, docking SBUS signal needs to invert the level in hardware, software inversion is invalid,
inversion circuit is as follows.
VCC3V3_MCU
RXD
Q1
1K
RC_SBUS
B
C
E
GND
10K
SBUS
Receivers
MCU
G
N
D
T R
X X
D D
VCC
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