20
1 START AND STOP
1.1 Start
• Signal state
*1 The interlock must be provided so that the buffer memory is accessed after Synchronization flag [X1] turns on. When no interlock is
provided, an unexpected value may be read or written.
Signal name Signal state Device
I/O signal PLC READY signal ON CPU module preparation completed Y0
READY signal ON RD77MS preparation completed X0
All axis servo ON ON All axis servo ON Y1
Synchronization flag
*1
ON The RD77MS buffer memory can be
accessed.
X1
Axis stop signal OFF Axis stop signal is OFF [Cd.180] Axis stop
M code ON signal OFF M code ON signal is OFF [Md.31] Status: b12
Error detection signal OFF There is no error [Md.31] Status: b13
BUSY signal OFF BUSY signal is OFF X10 to X1F
Start complete signal OFF Start complete signal is OFF [Md.31] Status: b14
External signal Forced stop input signal ON There is no forced stop input
Stop signal OFF Stop signal is OFF
Upper limit (FLS) ON Within limit range
Lower limit (RLS) ON Within limit range
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