Frequency Synthesis 2-7
Figure 2-3 UHF Synthesizer Block Diagram
Output LOCK (U5201-4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. IC U5201 provides the 16.8 MHz reference frequency at
pin 19.
The serial interface (SRL) is connected to the µP via data line DATA (U5201-7), clock line CLK
(U5201-8), and chip enable line CSX (U5201-9).
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U4211 PIN 1)
7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1
BIAS1
SFOUT
AUX3
AUX4
IADAPT
IOUT
GND
FREFOUT
LOCK
4
19
6, 22, 33, 44
43
45
3
2
28
14
15
40
FILTERED 5V
STEERING
LOCK (U0101 PIN 56)
PRESCALER IN
FREF (U0221 PIN 34)
39
BIAS2
41
48
5, 20, 34, 36
+5V (U4211 PIN 1)
AUX1
VDD, DC5V
MODOUT
U5201
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
AUX2
1 (NU)
BWSELECT
VCO Bias
TRB
To IF
Section
TX RF INJECTION
(1ST STAGE OF PA)
LO RF INJECTION
VOLTAGE
CONTROLLED
OSCILLATOR
LINE
2-POLE
LOOP
FILTER
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