Appendix A- 2
SPI bus consists of five signal lines. Refer to Appendix Table 1 for the
signal information. A communications failure between the host
processor and the Secure Module will be indicated as an “ERROR 09/
10” message on the radio display.
Appendix A Table 1. MTS 2000 Single Key Secure Module I/O Definition
SIGNAL NAME
CONNECTOR PLUG
P1 PIN NUMBER
FUNCTION
UNSW B+ 1 Unswitched battery voltage
Vdd 2 Switched 5 volt supply
2.1MHz REF CLK 3 2.1/2.4 MHz clock signal
GROUND 4 Ground
ASFIC PRE-EMP out 7 Transmit Clear Audio
AUX RX 9 Receive Clear Audio
DISCRIMINATOR 10 Receive Encrypted Audio
GROUND 11 Ground
RESET 12 Radio Reset - Does NOT reset module
KEY/FAIL 13 Keyloading Signal
TX AUDIO 14 Transmit Encrypted Audio
KEY INSERT DATA 15 Keyloading Signal
DVP WE 16 Keyloading Signal
SPI CLK 17 SPI Data Clock
SPI TX DATA (MOSI) 18 SPI Data from Host
SPI RX DATA (MISO) 19 SPI Data to Host
EXP INT1 20 SPI Secure Interrupt Request
EXP SEL1 21 SPI Secure Slave Select
CONT 5V 24 Continuous 5 Volt Regulator Output (Not Used)
5,6,8,22,23,25 Not Used
2
1
18
17
21
3
7
4
10
19
20
24
14
9
16
15
13
12
11
SPI CLK
UNSW B+ Vdd
SPI TX DATA (MOSI)
EXP SEL 1
2.1MHz REF CLK
ASFIC PRE-EMP out
DISCRIMINATOR
SPI RX DATA (MISO)
EXP INT 1
TX AUDIO
AUX RX
CONT 5V
DVP WE
KEY INSERT DATA
KEY/FAIL
RESET
Interface and Control
Encode / Decode
Key Variable Storage
Serial Peripheral Interface (SPI)
MAEPF-26127-O
Not Connected: 5,6,8,22,23,25
Appendix Figure 1. Secure Module
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