Motorola MC9S12DT256 User Manual

MC9S12DT256 Device User Guide — V03.07
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12DT256. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the
memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
For further explanation on the modes refer to the Core User Guide.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
ROMON
Bit
Mode Description
000X1
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
001
01
Emulation Expanded Narrow, BDM allowed
10
010X0
Special Test (Expanded Wide), BDM allowed
011
01
Emulation Expanded Wide, BDM allowed
10
100X1
Normal Single Chip, BDM allowed
101
00
Normal Expanded Narrow, BDM allowed
11
110X1
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
111
00
Normal Expanded Wide, BDM allowed
11
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS Description
1
Colpitts Oscillator selected

Motorola MC9S12DT256 Specifications

General

Brand	Motorola
Model	MC9S12DT256
Category	Microcontrollers
Language	English