Index
IN-2 Computer Group Literature Center Web Site
I
N
D
E
X
conductive chassis rails (EMC compliance)
A-4
configurable items, MVME162P4 board 1-5
configuration switches
S3 (Flash Write Enable mode) 2-7
S3 (MC2 DRAM size) 1-15, 2-7
S4 (EPROM/Flash selection) 2-9, 3-3
S4 (general-purpose readable switch)
1-17
S4 (software-readable switch) 2-5
S5 (IP DMA snoop control) 2-7
S5 (IP reset mode) 2-7
S5 pin 3 (IP reset mode) 1-19
S5 pin 4 (Flash write enable) 1-20, 4-11
S5 pins 1/2 (IP DMA snoop control)
1-18
S6 (MCECC DRAM size) 1-21, 2-7
configuration switches, location of 1-5
Configure Board Information Block (CNFG)
firmware command 3-9
configuring
162Bug parameters 3-11
hardware 2-5
IndustryPack modules 3-19
IP base addresses 3-19
VMEbus interface 3-16
connection diagrams
EIA-232-D 1-29
EIA-530 1-35
connector pin assignments 5-1
connectors 4-19
IndustryPack (IP) 1-23
console port 2-7
control/status registers 1-27
controller LUN (CLUN) C-1, D-1
controller modules (disk/tape) D-1
controller modules (network) C-1
cooling requirements A-2
CSR bit IP32 (IP bus clock) 1-8
D
data bus structure, MVME162P4 4-6
data circuit-terminating equipment (DCE)
4-13
data sheets E-2
date and time, setting 2-8, B-2
DCE (data circuit-terminating equipment)
4-13
debugger
commands 3-6
firmware (162Bug) 3-9
prompt 3-5
default baud rate 2-8
device LUN (DLUN) C-1, D-2
diagnostic facilities 2-14
dimensions, base board A-1
direct access devices D-4
direct memory access (DMA) 4-15
directories, switching 2-14
disk/tape controller modules supported D-1
DLUN (device LUN) C-1, D-2
DMA (direct memory access) 4-15
DRAM (dynamic RAM)
base address 1-26
options 4-7
E
EIA-232-D
connection diagrams 1-29
ports 2-7
SIM part numbers 1-10
EIA-485/EIA-422
connection diagrams 1-37
EIA-530
connection diagrams 1-35
EIA-530/V.36 SIM part numbers 1-10
EMC regulatory compliance A-4
ENV command parameters 3-11
environmental parameters 3-9
EPROM 3-3
and Flash memory 4-11
size select header (J23) 1-14
socket 4-11
EPROM/Flash selection (S4) 1-17
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