Topaz T2688/T200, T2988/T205 L3 Circuit Description
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Motorola Proprietary Information
16. Within the VEGA IC the path of the base-band RXI & Q data from the TX / RX IC
takes the following route.
17. The RXI and Q signals from the RX/TX IC enter the VEGA IC (BDLIP / BDLIN /
BDLQP / BDLQN) and follow identical paths. The first stage is through a
continuous-time second order anti-aliasing filter, which serves 2 functions: 1) to
interface between RF logic and on-chip circuitry and 2) to prevent aliasing during the
ADC process.
18. The signal is then fed into a Sigma – Delta ADC sampling at 6.5MHz, and is fed out
as a 3-bit word. This is then fed into a set of digital filters, that will decimate (break
the signal into piece parts) to give us an overall sampling rate of 270.8KHz (?24).
This gives us a low enough frequency for adjacent channel rejection and therefore
channel separation.
19. Calibration of the IQ paths is achieved by internally shorting out the 2 input I paths,
and then the same again on the 2 input Q paths the digital value measured will then be
stored in a register. Once the RXI and Q paths are reconnected to the circuitry, again
the calibration process takes place and the offset value is calculated.
20. From the VEGA IC, the information is looped through to the GEMINI IC on the
Base-band serial interface, consisting of BDX, (Base-band Data Transmit) BCLKX
(Base-band Transmit Clock) and BFSX (Base-band Transmit Frame synch). See
below for timing diagram:
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