Topaz T2688/T200, T2988/T205 L3 Circuit Description
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Motorola Proprietary Information
85. This will began to charge the battery through BQ3. (BQ3 fully open) The voltage
divider R111 and R112 puts a voltage of 4V onto the source of BQ6. During this time
C81 will be charged (approximate charging time is 3 – 5 Seconds.
86. When the charge in C81 reaches 4V the, the S-G bias on BQ6 will be 0V, which will
effectively turn off BQ6, this in turn has the effect to switch Charging Control IC U29
off which will turn off BQ3.
87. For Normal charge the phased charging values stored in the EEprom will be D/A’d
then sent as signal IO11 which will control the gate of Charging Control IC U29
which will vary the gate of BQ3. This allows us to vary the charge onto the battery.
88. An exception to the above exists if a car kit is being used in which case, Ext. Power
will be input into the phone on the I/O connector Pin 11, with U19 provide ESD
protection as the signal IOPN11.
89. It will then be fed through Fuse F2, and onto the source (S1) of Dual FET U26, the
amount of current that is passed through to VBAT is controlled via software IO1 by
U25
90. For Power output when using the data cable, VBAT is fed onto the source (S2) of
U26, with U29 providing gate bias. D12 is forward biased for this 1 application.
91. The real time clock is generated by crystal X2 and runs at 32.768MHz. It is driven by
the charge pump from U46 Pin 1 (OSC1).
Synchronisation is achieved by IO14, which is clock generated by Gemini pin 50,
with the IC enabled by Chip Enable RTCCE Gemini Pin 117.
The re-chargeable RTC battery U32 provides power for U46. As mentioned in Point
74.
Pin3 nINT provides the alarm interrupt to power the unit on at a specified time.
92. U47 is the 1.8V regulator used to Power Gemini, supported by VBAT and is powered
on at the same time as the Power Control IC U27 (Pin 1 CTRL) and is supported by
VBAT. The 1.8V regulated voltage is fed out to the Gemini as PVCC18.
Memory
93. Flash U23 is split into Operating Software memory 12Mbit and EEprom Memory
4Mbit. Supported by DVCC on Pin G4. Chip enable NROMCS (N signifies active
low) from Gemini Pin 17 onto Flash Pin F1. Boot-code is contained within the IC
NFOE, Pin G1 (Active Low Flash Output Enable) is used to instruct Flash that
Gemini want to read or write form the device. DLPWR is not used.
94. SRAM U22 is a 2Mbit device, supported by DVCC on Pin E1. SRAM is Chip
enabled by NRAMCS Pin G3.
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