En-27
Englsh
OC Gene
Settng ths tem to [Enabled] allows the system to detect the maxmum FSB clock and
to overclock automatcally. If overclockng fals to run, you can try the lower FSB clock
for overclockng successfully.
AMD Turbo Core Technology
Ths technology automatcally ncreases the frequency of actve CPU cores to mprove
performance.
Adjust Turbo Core Rato
Ths tem s used to adjust turbo core rato.
IGD Engne CLK
Ths tem s used to adjust ntegrated graphcs clock.
DRAM Frequency
Ths tem s used to adjust the DRAM frequency. Settng to [Auto], the system wll detect
the DRAM Frequency automatcally.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect)
EEPROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the
followng “Advanced DRAM Conguraton” sub-menu to be determned by BIOS based
on the conguratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to congure
the DRAM tmngs and the followng related “Advanced DRAM Conguraton” sub-menu
manually.
Advanced DRAM Conguraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsucent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
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