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MSI MEG Z590 UNIFY-X

MSI MEG Z590 UNIFY-X
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35
Overview of Components
PCIe bandwidth configuration table for PCIe & M.2 slots
The M2_2 and M2_3 slots can be used under two PCIe bandwidth modes: Chipset
mode (default) and CPU mode (by BIOS setting). Please refer the PCIe bandwidth
configuration table below for details.
Slot Chipset mode (Default)
CPU mode (By BIOS setting)
PCI_E1 3.0 x1 3.0 x1
PCI_E2 4.0* x16 or 3.0 x16 4.0* x8 or 3.0 x8
PCI_E3 3.0 x1 3.0 x1
PCI_E4 3.0 x4 3.0 x1 3.0 x4 3.0 x1
M2_1
4.0 x4
(M2_1 slot is available only on 11th Gen Intel® CPU)
M2_2 3.0 x4 4.0* x4 or 3.0 x4
M2_3 3.0 x4 4.0* x4 or 3.0 x4
M2_4 3.0 x4 3.0 x2 3.0 x4 3.0 x2

* PCIe 4.0 specification is available only on 11th Gen Intel® CPU.
Important
Enabling CPU mode for M2_2 & M2_3 slots, please go to BIOS > SETTINGS > Advanced
> PCIe/PCI sub-system Settings > CPU PCIe Lanes Configuration and configure the
PCIe Lanes to x8/x4/x4 for PCI_E2, M2_2 and M2_3 slots first. In CPU mode, the
PCI_E2, M2_2 and M2_3 slots share the same PCIe bandwidth.

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