3-24
MS-7514 Mainboard
tRCD
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS
(row address strobe) to CAS (column address strobe). The less the clock
cycles, the faster the DRAM performance.
tRP
This setting controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refresh may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system.
tRAS
This setting determines the time RAS takes to read from and write to memory
cell.
1N/2N Memory Timing
This item controls the SDRAM command rate. Select [1N] makes SDRAM signal
controller to run at 1N (N=clock cycles) rate. Selecting [2N] makes SDRAM signal
controller run at 2N rate.
Advance Memory Setting
Setting to [Auto] enables the advance memory timing automatically to be determined
by BIOS. Setting to [Manual] allows you to set advanced memory timings.
TRFC
When the Adcance Memory Setting sets to [Manual], the field is adjustable.
This setting determines the time RFC takes to read from and write to a memory
cell.
TWR
When the Adcance Memory Setting sets to [Manual], the field is adjustable.
Minimum time interval between end of write data burst and the start of a precharge
command. Allows sense amplifiers to restore data to cells.
TWTR
When the Adcance Memory Setting sets to [Manual], the field is adjustable.
Minimum time interval between the end of write data burst and the start of a
column-read command. It allows I/O gating to overdrive sense amplifiers before
read command starts.
TRRD
When the Adcance Memory Setting sets to [Manual], the field is adjustable.
Specifies the active-to-active delay of different banks.
To Next Page
Loading...
