MSI MS-7793 - Page 48

En-36
MS-7793 Manboard
tCL
Controls CAS latency whch determnes the tmng delay (n clock cycles) of startng
a read command after recevng data.
tRCD
Determnes the tmng of the transton from RAS (row address strobe) to CAS
(column address strobe). The less clock cycles, the faster the DRAM performance.
tRP
Controls number of cycles for RAS (row address strobe) to be allowed to pre-charge.
If nsu󰘲cent tme s allowed for RAS to accumulate before DRAM refresh, the DRAM
may fal to retan data. Ths tem apples only when synchronous DRAM s nstalled
n the system.
tRAS
Determnes the tme RAS (row address strobe) takes to read from and wrte to
memory cell.
tRTP
Ths tem s used to adjust the tme nterval between a read and a precharge
command.
tRC
The row cycle tme determnes the mnmum number of clock cycles a memory row
takes to complete a full cycle, from row actvaton up to the prechargng of the actve
row.
tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense ampl󰘰ers to restore data to cells.
tRRD
Spec󰘰es the actve-to-actve delay of d󰘯erent banks.
tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a
columnread command. It allows I/O gatng to overdrve sense ampl󰘰ers before read
command starts.
tRFC0/ 1
These settngs determne the tme RFC0/1 takes to read from and wrte to a memory
cell.
Advanced Channel 1/ 2 Tmng Con󰘰guraton
Press <Enter> to enter the sub-menu. And you can set the advanced memory tmng
for each channel.
CPU Core Vdroop O󰘯set Control
Ths tem s used to select the CPU core Vdroop o󰘯set control mode.
CPU NB Vdroop O󰘯set Control
Ths tem s used to select the CPU-NB Vdroop o󰘯set control mode.
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