MSI P35 NEO2-FR - Motherboard - ATX - Page 60

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MS-7345 Mainboard
Configuration DRAM Timing by SPD
Setting to [Enabled] enables DRAM CAS# Latency automatically to be determined
by BIOS based on the configurations on the SPD (Serial Presence Detect) EEPROM
on the DRAM module.
DRAM CAS# Latency
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable.This controls the CAS latency, which determines the timing delay (in
clock cycles) before SDRAM starts a read command after receiving it.
DRAM RAS# to CAS# Delay
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the transition
from RAS (row address strobe) to CAS (column address strobe). The less the
clock cycles, the faster the DRAM performance.
DRAM RAS# Precharge
When the Configuration DRAM Timing by SPD sets to [Disabled], this field is
adjustable. This setting controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete and
DRAM may fail to retain data. This item applies only when synchronous DRAM is
installed in the system.
DRAM TRFC
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. This setting determines the time RFC takes to read from and write to
a memory cell.
DRAM TWR
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Minimum time interval between end of write data burst and the start
of a precharge command. Allows sense amplifiers to restore data to cells.
DRAM TWTR
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Minimum time interval between the end of write data burst and the
7345v1.0-3_BIOS.p65 2007/5/17, 上午 11:2822