BEC
RPR 550IS Series
TM1188 Issue 1 Page 3 - 13
Decoder Operation
36. The radio receiving circuits are activated for a brief period once a second by so
that IC2 can check for the presence of the Mk7 preamble signal (256Hz square wave).
If preamble is detected, the radio receiving circuits remain powered on and IC2 is used
to acquire batch synchronisation. When synchronisation has been achieved, IC2 starts
to generate interrupts from its DTI output (pin 66) which are applied to the
microprocessor IC3 INT4 input (pin 32) every 62.5ms (32 bit periods). After each
interrupt the microprocessor collects the 32 data bits in 4 bit words using the parallel
data bus between IC2 and IC3. The bus comprises DA0-DA3 (pins 35-38) on the gate
array (IC2) and P60-P63 (pins 7, 6, 5 and 4) on the microprocessor (IC3).
37. The data collected from IC2 is decoded using software in the microprocessor and if a
call is recognised an alert is generated comprising audible tone alert, flashing LED, text
displayed on the LCD and optionally speech and/or vibration.
Clocks
38. The two clocks on the main board control the timing of the gate array and the
microprocessor. The gate array clock XL3 runs at 32.768kHz and the microprocessor
clock XL4, at 1MHz.
Speech Enable
39. The SPEECHEN signal is generated from pin 8 of IC3 and gates on amplifier TR10 via
R39.
Visual Alert LED
40. The high output Light Emitting Diode (LED), D3, is driven by TR17. A low signal from
LP2, pin 21 of IC2, enables TR17 allowing current from V
DD
to pass to the LED and
turn it on.
Audible Alert Drive Circuit
41. The beep signal which is generated in gate array IC2 has its cadence controlled by
microprocessor IC3. The signal from pin 13 of IC2 is amplified by TR24 and TR20
before being applied to the transducer L3. The inductance of its coil is tuned by C22,
thereby maximising the output signal. Resistor R15 is an IS component and provides
infallible isolation of the power available from R16 to the transducer and driver from the
rest of the circuitry.
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