NAD T 742 - Page 32

VCC
DATA OUTPUTS
O0 - O7
OE, CE AND
PROGRAM LOGIC
Y DECODER
X DECODER
OUTPUT
BUFFERS
Y-GATING
IDENTIFICATION
CELL MATRIX
GND
VPP
OE
CE
A0 - A18
ADDRESS
INPUT
44
AMPLIFIER 1
OUTPUT
INVERTING
INPUT
NON-INVERTING
INPUT
V –
AMPLIFIER 2
V +
OUTPUT
INVERTING
INPUT
NON-INVERTING
INPUT
1
2
3
4
8
7
6
5
+ – – +
AC3 BOARD
U106, U107: 74HC574
D7
DQ
CP
FF8
Q7
D6
DQ
CP
FF7
Q6
D1 D2 to D5
DQ
CP
FF2
Q1
D0
CP
OE
DQ
CP
FF1
Q0
AC3 BOARD
U108: AT27C040
27
36 8-11,14-17 18 5 4 19 7 6 20 21
37
38
44
43
42
41
40
39
3
28
29
25
26
22
30
31
32 33 34 35 2 13 24 1 12 23
Parallel or Serial Host Interface
24-Bit
DSP Processing
Framer
Shifter
Input
Buffer
Controller
Compressed
Data Input
Interface
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLK1N
CLKSEL
FILT2 FILT1 VA AGND DGND[1-3] VD[1-3]
XMT958
AUDATA2
AUDATA1
AUDATA0
LRCLK
SCLK
MCLK
DC
DD
EXTMEM,
GPIO8
ABOOT,
INTREQ
A1,
SCDIN
A0,
SCCLK
SCDIO,
SCDOUT,
PSEL,
GPIO9
WR,
DS,
EMWR,
GPIO10
RD,
R/W,
EMOE,
GPIO11
CS
DATA7-0,
EMAD7-0,
GPIO7-0
RESET
Digital
Audio
Input
Interface
PLL
Clock Manager
RAM Input
Buffer
RAM
Program
Memory
RAM
Program
Memory
RAM
Output
Buffer
Output
Formatter
RAM
Program
Memory
RAM
Program
Memory
STC
AC3 BOARD
U105: CS9426
AC3 BOARD
U104, U109, U116, U134: NJM5532
U131: NJM4558D