National Instruments myRIO-1950 - Connector Pinouts

4.0 FPGA Pinnout and UCF File:
The following is a snapshot of a UCF file that defines the pinnout of the FPGA portion of the Zynq. Note
that some of these pins are a part of SPI ports and an I2C port that goes to the onboard Dacs, ADCs, and
accelerometer. These ports have timing requirements that are also included in this UCF snapshot.
##################################################################################
##################################################################################
#Top Level Clock
NET "Clk40" LOC = K17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #40Mhz clock, Input
#User IO
NET "aUserSwitch_n" LOC = F17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #BUTTON0, Input
NET "cFpgaLed[0]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #LED0, output
NET "cFpgaLed[1]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #LED1, output
NET "cFpgaLed[2]" LOC = T19 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #LED2, output
NET "cFpgaLed[3]" LOC = R19 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #LED3, output
#Processor Reset
NET "system_reset_n" LOC = J15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
#Accelerometer (MMA8452)
NET "aAccelScl" LOC = H17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAccelSda" LOC = K18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aAccelInt_n" LOC = L17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
#ADC (ADS7952)
NET "aAiSpiCs_n" LOC = F20 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAiSpiClk" LOC = F19 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAiSpiMosi" LOC = G18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAiSpiMiso" LOC = G17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input
#DACs (DAC7562SDSC).
#There are 2 Dac devices selectable with the Cs[0] and Cs[1] pins.
#Note how this logic is inverted logic from a typical SPI port.
NET "aAoMxpSpiMosi_n" LOC = G20 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAoMxpSpiClk_n" LOC = G19 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAoMxpSpiCs[0]" LOC = G15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAoMxpSpiCs[1]" LOC = H15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
NET "aAoMxpLdac" LOC = N16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #output
#MXPA DIO
NET "aMxpAdio0" LOC = V12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio1" LOC = T10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio2" LOC = U12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio3" LOC = R14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio4" LOC = T12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio5" LOC = U18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio6" LOC = W13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output
NET "aMxpAdio7" LOC = T15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output