Chapter 2 Theory of Operation
PCI E Series RLPM 2-12
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National Instruments Corporation
appropriate bit in a register in the PCI E Series register set. Any one of
these operations will generate the timing shown in Figure 2-8.
Figure 2-8. ADC Timing
When SHIFTIN* shifts the ADC value into the ADC FIFO buffer, the
AI_FIFO_Empty_St bit in the status register is cleared, which indicates
that valid data is available to be read. Single conversion timing of this type
is appropriate for reading channel data on an ad hoc basis. However, if you
need a sequence of conversions, the time interval between successive
conversions is not constant because it relies on the software to generate the
conversions. For finely timed conversions that require triggering and
gating, you must program the boards to automatically generate timed
signals that initiate and gate conversions. This is known as a data
acquisition (DAQ) sequence.
Data Acquisition Sequence Timing
The following counters are used for a data acquisition sequence:
• Scan interval (SI) 24 bits
• Sample interval (SI2) 16 bits
• Divide by (DIV) 16 bits
• Scan counter (SC) 24 bits
This section presents a concise summary of only the most important
features of your board. For a complete description of all the analog input
modes and features of the PCI E Series boards, refer to the DAQ-STC
Technical Reference Manual.
The most basic timing signal in the analog input model is the CONVERT*
signal. A group of precisely timed CONVERT* pulses is a SCAN. The
sequence of channels selected in each conversion in a SCAN is
programmed in the configuration memory prior to starting the operation.
The SI2 counter is a 16-bit counter in the DAQ-STC. This counter
CONVERT*
ADC_BUSY*
SHIFTIN*
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