SYSTEM TECHNICAL MANUAL
HARDWARE DESCRIPTION
Direction In
This signal defines direction of motion of the R/W head when
the Step line is pulsed. A logical zero defines the direction as
“out” and if a pulse is applied to the Step line, the R/W
heads will move away from the center of the disk. If this line
is a logical one, the direction of motion is defined as “in” and
the R/W heads will move toward the center of the disk. Di
rection must not change during step time.
Step
This interface line is a control signal which causes the R/W
head to move with the direction of motion defined by the
Direction In line. Any change in the Direction In line must be
made at least 100ns before the leading edge of the step pulse.
The buffered seek mode is automatically selected any time
step pulses are issued at a rate between 25 and 500
jisec. The
minimum time between successive steps is 3.0mS. In the slow
step mode, the R/W heads will move at the rate of the in
coming step pulses.
Drive Select 1-4
Drive Select, when a logical one connects the drive interface
to the control lines and activates the LED on the front panel
of the drive. Shunts are provided on the drive which can be cut
in a specified pattern so as to determine which unique select
line (DS1-4) on the interface will activate that particular drive.
MFM Write Data
This is a differential pair that defines the transitions to be
written on the track. The transition of +MFM Write Data line
going more positive than the -MFM Write Data will cause a
flux reversal on the track, provided Write Gate is active. This
signal must be driven to an inactive state (+MFM Write Data
more negative than -MFM Write Data) by the host system
when in a read mode.
To ensure data integrity at ti e error rate specified, the
write data presented by the host must be pre-compensated on
tracks 128 through 305. Data patterns which cause a large
amount of bit shift will have appropriate data bits shifted early
or late with respect to the nominal bit cell position. Bit shift
compensation, whether early or late with respect to the
nominal bit cell position, will be 12ns.
2-29
To Next Page
Loading...