NCR Decision Mate V - Page 80

a
c
+5 V
1
+5 V
IRQ
2
RESET/
3
IOW/
4
5
IOR /
BD1
6
BDO
BD3
7
BD2
BD5
8
BD4
BD7
9
10
11
12
13
14
BD6
15
CLK1
LGRD
16
17
18
19
20
21
22
23
24
25
BA1
26
27
BAO
28
29
30
31
IFSELO/
LGRD 32
LGRD
Figure 2.44 Centronics pin assignments
The signals to and from the adapter are standard TTL level.
The rise and fall time of the signals must be less than 0.2/tsec. The
interface timing is shown in Figure 2.45.
The Centronics interface signals are defined in Figure 2.46.
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