2-8 Central Processor Unit (CPU) circuit pack (NT6M62BA)
297-1001-539 Standard 01.03 September 2000
Table 2-2
CPU display control functions
Mode SW2-3 SW2-4 Description
Monitor Error
Control Port
on off Standard setting: data written to the error control
port I/01 (88-8B; hex) is decoded, along with
processor signals WAIT, HALT, RESET, BUSAK,
and CLK
Independent
Port (invalid)
off on Data must be written to I/06 (9C-9F; Hex). This is
included for future use. Display codes must be
modified by changing the decoder firmware.
Both Ports
(invalid)
on on This is an invalid condition since data written to
either port may be displayed.
Neither Port
(invalid)
off off No data is written to the display circuit, causing
an error condition display = E.
Table 2-3
CPU with DMA circuit pack (A1 and B1) options - part number: NT6M62BA
Device type
number
Position/setting Function Setting
Factory On-site
Jumper
(J3)
1
PINS:
2-3
1-2:
8 KHz clock from DMS-
100 enabled.
60 Hz clock from AC
adapter, if present.
Determines whether the
DPP uses 8 KHz from the
DMS-100 or the optional ac
clock.
1-2
pin 1 is
closest to
gold finger
contact.
Jumper
(JU1)
1
In:
Out:
Enable 8KHz clock
receiver.
Disable 8KHz clock
receiver.
Control operation of 8KHz
clock receiver.
In
Jumper
(JU2)
All Enable additional wait
states.
Enable the addition of wait
states (up to 5) on the
ABCD inputs of the counter
chip.
Configuredf
or 1 wait
state in the
copper
tracings
Jumper
(JU3 &JU4)
Out: Connects the internal
8KHz to pin 85 of the
backplane connector.
Attachment of peripherals;
not defined at this time.
Out
(Currently
unused)
Strap None used
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