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DPP Hardware Component Replacement Guide DPP001 and up
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56K Interface circuit pack (NT6M94xx) -
Turbo only
General description
The 56K Interface circuit pack in slot 7 provides a dual serial communication
interface function for the DPP. This circuit pack uses a Serial
Communication Controller (SCC) chip which lets the DPP transmit and
receive serial data at various standard software selectable programmed rates
from 1200-9600 bps on channel A and 56K bps on channel B.
56K Interface circuit pack communication with the Main Processor (MP), in
slot 1, is based on a polling strategy as opposed to an interrupt scheme. Two
FIFO (First In-First Out) buffers provide a bidirectional path between the 56K
Interface circuit pack and MP.
The SCC port consists of an SCC chip (at U36) along with a bus interface
section and CPU interface section. The SCC has a 9.8304 MHz clock from
which it derives timing for SCC bus activity and SIO baud rates. A separate
clock is used because the clock available on the circuit pack (12 MHz)
exceeds chip capability. The 6MHz (12 MHz divided by two) provided by the
CPU is too slow for adequate SCC response.
Table 7-1 shows the five option jumpers on the circuit pack. Figure 7-1 shows
jumper locations and circuit pack layout.
The 56K Interface circuit pack requires +5 V dc +/- 0.25 volts. This is
accomplished by the 5 volt regulator on the circuit pack which uses the +8.5
V dc supply from the backplane.
The 56K Interface circuit pack capabilities and functions include:
• Interface between DPP system backplane and 56K Crossover circuit pack.
• 512 bytes of bidirectional FIFO RAM for data passing to/from main CPU.
• Noninterrupt driven (polled) data and command port implementation
allowing installation in any DPP COM (A7 and B7 used) slot without any
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