Onkyo TX-SR504E - IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-6; Terminal Description (3;4)

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-6
Q201 : D707E001RFP250 (32 bit Floating-Point Digital Signal Processor)-6/7
TERMINAL DESCRIPTION (3/4)
TX-SR504/504E/8450
PIN
SIGNAL NAME TYPE PULL GPIO DESCRIPTION
NO.
AHCLKR0/AHCLKR1 143 IO - Y
ACLKR0 139 IO - Y
AFSR0 141 IO - Y
AHCLKX0/AHCLKX2 2 IO - Y
ACLKX0 142 IO - Y
AFSX0 144 IO - Y
AMUTE0 3 O - Y
AXR0[0] 113 IO - Y
AXR0[1] 115 IO - Y
AXR0[2] 116 IO - Y
AXR0[3] 117 IO - Y
AXR0[4] 119 IO - Y
AXR0[5]/SPI1_SCS 120 IO - Y
AXR0[6]/SPI1_ENA 121 IO - Y
AXR0[7]/SPI1_CLK 122 IO - Y
AXR0[8]/AXR1[5]/
126 IO - Y
SPI1_SOMI
AXR0[9]/AXR1[4]/
127 IO - Y
SPI1_SIMO
AXR0[10]/AXR1[3] 130 IO - Y
AXR0[11]/AXR1[2] 131 IO - Y
AXR0[12]/AXR1[1] 134 IO - Y
AXR0[13]/AXR1[0] 135 IO - Y
AXR0[14]/AXR2[1] 137 IO - Y
AXR0[15]/AXR2[0] 138 IO - Y
ACLKR1 9 IO - Y
AFSR1 12 IO - Y
AHCLKX1 5 IO - Y
ACLKX1 7 IO - Y
AFSX1 11 IO - Y
AMUTE1 4 O - Y
SPI0_SOMI/I2C0_SDA 111 IO - Y
SPI0_SIMO 110 IO - Y
SPI0_CLK/I2C0_SCL 108 IO - Y
SPI0_SCS/I2C1_SCL 107 IO - Y
SPI0_ENA/I2C1_SDA 105 IO - Y
McASP0, McASP1, McASP2, and SPI1 Serial Ports
SPI0, I2C0, and I2C1 Serial Port Pins
McASP0 and McASP1 Receive Master Clock
McASP0 Receive Bit Clock
McASP0 Receive Frame Sync (L/R Clock)
McASP0 and McASP2 Transmit Master Clock
McASP0 Transmit Bit Clock
McASP0 Transmit Frame Sync (L/R Clock)
McASP0 MUTE Output
McASP0 Serial Data 0
McASP0 Serial Data 1
McASP0 Serial Data 2
McASP0 Serial Data 3
McASP0 Serial Data 4
McASP0 Serial Data 5 or SPI1 Slave Chip Select
McASP0 Serial Data 6 or SPI1 Enable (Ready)
McASP0 Serial Data 7 or SPI1 Serial Clock
McASP0 Serial Data 8 or McASP1 Serial Data 5 or
SPI1 Data Pin Slave Out Master In
McASP0 Serial Data 9 or McASP1 Serial Data 4 or
SPI1 Data Pin Slave In Master Out
McASP0 Serial Data 10 or McASP1 Serial Data 3
McASP0 Serial Data 11 or McASP1 Serial Data 2
McASP0 Serial Data 12 or McASP1 Serial Data 1
McASP0 Serial Data 13 or McASP1 Serial Data 0
McASP0 Serial Data 14 or McASP2 Serial Data 1
McASP0 Serial Data 15 or McASP2 Serial Data 0
McASP1 Receive Bit Clock
McASP1 Receive Frame Sync (L/RClock)
McASP1 Transmit Master Clock
McASP1 Transmit Bit Clock
McASP1 Transmit Frame Sync (L/RClock)
McASP1 MUTE Output
SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
SPI0 Data Pin Slave In Master Out
SPI0 Serial Clock or I2C0 Serial Clock
SPI0 Slave Chip Select or I2C1 Serial Clock
SPI0 Enable (Ready) or I2C1 Serial Data