ORTEC 473 - Lower Level Discriminator; Upper Level Threshold; Constant Fraction Discriminator

5.2. INFMJT CIRCUIT
Signals are accepted through CN1. The input is protected against large amplitude signals by Q1, D1, and D2. Resistor R42
provides SOfi termination for the input signals and divides the input amplitude by a factor of 2. The input signals can be
monitored at TP1 on the front panel.
The signals are furnished through R45 and buffer Q5 into the lower level discriminator and through R75 and buffer Q7 into
the upper level discriminator. The signals are also furnished through DL14 and DL15 into the constant fraction discriminator
circuit.
5.3. LOWER LEVEL DISCRIMINATOR
The signal through 05 is furnished to pin 9 of IC2A and its level is compared to a reference level at pin 10. Under quiescent
conditions, the level at pin 9 is less negative than that at pin 10. When the level at pin 9 exceeds the level at pin 10, IC2A
changes state and generates a response, LLLE for lower level leading edge, used to reset the internal logic and to arm a zero
crossing discriminator in the constant fraction circuit. The response remains until the input signal level decays through the
reference level.
The reference level at pin 10 is furnished from the upper level adjustment through R43 and R73 and is about 50% of the
upper level threshold. A calibrated baseline is furnished from R160 and R65 through Q4.
5.4. UPPER LEVEL THRESHOLD
The signal through Q7 is furnished to pin 9 of IC4A and its level is compared to a reference level at pin 10. Under quiescent
conditions, the level at pin 9 is less negative than that at pin 10. When the level at pin 9 exceeds the level at pin 10 because of
the input signal amplitude, IC4A changes state and generates a response, ULLE for upper level leading edge, used to permit an
output signal to be generated. The response remains until the input signal level decays through the reference level.
The reference level at pin 10 is furnished from the R66, R67, R69 circuit through Q6. The range is calibrated by R66 for the
front panel level control, R67. The effective range, referred to the input, is 50 mV through 5 V.
5.5. CONSTANT FRACTION DISCRIMINATOR
Each input signal is applied to two parallel circuits. One circuit delays the input pulse and the other circuit attenuates the
signal. The delay circuit switch-selects DL1, DL2, or DL3 for Ge(Li), Scint, or Nal respectively, or an external circuit through
DL4 and DL5 plus whatever amount of delay is connected between the rear panel BNC connectors. The attenuator circuit
selects R7 id R14 for Ge(Li), R8 and R15 for Scint, or R9 and R16 for the Nal mode; any of these selections provides dc
fraction of 32%. The value of the dc fraction is always greater than the effective fraction, f, because of inherent circuit delays.
If the switch selects Ext, the attenuator uses RIO through R13 and can be set at any of three fractions with an internal
jumper. The jumper is connected for a fraction of 30% when the unit is shipped, and can be changed to either 20% or 10% if
desired.
A differential comparator, IC1A, accepts the two signals through buffers Q2 and Q3, and determines the crossover time at
which the delayed signal amplitude exceeds the prompt attenuated signal amplitude. Since both signals are the result of the
same input pulse, the actual peak amplitude, within a normal range, does not affect the relative time at which the signal is
recognized.
The only portion of the input pulse the is used for Constant Fraction timing derivation is the rise time. Figure 5.1 shows how
two pulses with different peak amplitudes will generate identical timing responses in 101 A; the delayed signal is furnished to
pin 10 and the attenuated signal to pin 9. When the negative amplitude at pin 10 exceeds the amplitude at pin 9, IC1A
switches states and does not switch back until this condition is reversed at the end of the input pulse decay. The result is that
the C. F. Trigger response time is precisely the same for any original pulse amplitude within the normal response range for the
473. The pulse that is formed in 101A is shaped in 101B and 1010 and furnished to gate I03A, and the circuit is stabilized by
the feedback through Q10 and Q11 and through Q8 and Q9; R35 is a walk adjust control that sets the 0. F. baseline to
minimize time differences.
The optimum fraction in the 473 is furnished by an attenuator that divides the input amplitude by the proper ratio. The
appropriate delay is selected according to the normal rise time of the input pulses, and this varies from one type of detector
to another. The delay for Ge(Li) uses 9'4" of 50n cable for a delay of 14 ns; the delay for Scint uses 10-1/8" of cable for 1.3