ORTEC 473 - Constant Fraction Operation; Slo R.T. Rej Operation

Pulse A
Delaved
Attenuated
Delayed
Attenuated
Trigger Time
Fig. 5.1. Constant Fraction Trigger Timing for Two Different Input Pulse Amplitudes.
ns; the delay for Nal uses 15-1/4" of cable for 1.9 ns. In the external circuit, DL4 and DL5 are each 10" of cable, so the total
delay Is 3 ns plus whatever amount Is added between the rear panel connectors.
A timing pulse at pin 12 of IC3A Is generated In response to a negative-going Input variation at CN1, whether this Is a real
signal of Interest or It Is simply a small-amplitude pulse — generally noise — that Is to be disregarded. Gate IC3A will have
been aimed I > pass the timing signal by an LLLE response for a signal of Interest.
5.6. CONSTANT FRACTION OPERATION
Figure 5.2 Is a simplified block diagram of the 473 that shows selection of the C.F. mode of operation. A complete block
r' iqram, 473-0101-B1, Is Included at the back of the manual.
Constant fraction discrimination provides a timing pulse for each Input signal variation, whether It Is converted Into an output
signal or not. The function described In Section 5.5 uses the CP stage In Fig. 5.2 to accomplish this signal generation. If the
signal Is of Interest, It will have triggered the LLLE discriminator prior to the timing pulse so gate G1 (In Fig. 5.2) Is armed to
pass the timing pulse.
After a delay of about 29 ns, during which other acceptance criteria are checked, the timing pulse Is furnished to gate G2 (In
the schematic, this Is IC3B). A response In the ULLE circuit must have triggered FF IC6B-IC6C to Indicate that the Input
signal amplitude Is sufficient to satisfy the amplitude requirements, and the timing signal passes through G2 and G3 to trigger
an output one-shot, IC10A-IC10B, and generate the group of three output signals.
5.7. SLO R.T. REJ OPERATION
Operation with the Slow RIsetlme Reject circuit Is the same as for the Constant Fraction operation discussed In Section 5.6
except that the timing signal Is blocked at gate G3 (Fig. 5.2) If the signal rise time Is too slow. The SRT (slow rise time)
flip flop, IC7B-IC7C, Is reset by LLLE and Is enabled, through IC8D, to be set by FF IC6B-IC6C. The SRT flip-flop must
have been set by the time the timing pulse reaches G3 (IC9A) or the timing pulse wil l not pass; the presumption Is then that
the rise time of the Input pulse was too slow to qualify It as a true signal. The maximum rise time from LLLE to ULLE Is
about 25 ns to permit the output pulse generation to occur.