Panasonic CQ-DF783U - Page 13

Pin
No.
Port Descriptions I/O (V)
70 CVSS7 GND - 0
71 MCLK Clock output (To Servo
DSP)
O 3.3
72 DVSS4 GND - 0
73 MLD Command load signal
output (To Servo DSP)
I 3.3
74 MDATA Command data output (To
Servo DSP)
O 3.3
75 DVDD4 I/O system (3.3V) power
supply
- 3.3
76 DVSS5 GND - 0
77 - Clock mode setting (L
fixation)
I 0
78 - Clock mode setting (H
fixation)
I 3.3
79 - Clock mode setting (L
fixation)
I -
80 - - - -
81 SW2 Mechanics deck SW2 input I 0
82 - - - -
83 - - - -
84 - - - -
85 - - - -
86 - - - -
87 - - - -
88 - - - -
89 - - - -
90 CVSS8 GND - 3.3
91 CVDD5 CORE CPU system (1.6V)
power supply
- 0
92 (GND) GND I 1.6
93 DVSS6 GND - 0
94 - - - -
95
CLKENA
Oscillation output Cainabl
signal
O 3.3
96 ×1 Crystal Connection O 0
97 ×2 Crystal Connection I 0
98 (VDD) Reset signal input I 1
99 D0 Data base of FLASH ROM I/O 3.4
100 D1 I/O 0
101 D2 I/O 0
102 D3 I/O 0
103 D4 I/O 0
104 D5 I/O 0
105 A16 Address bus of FLASH ROM O 0
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