Panasonic CQ-VD6503W - Page 17

Pin
No.
Port Description I/O Vol
(V)
71 TFT SO/
TFT COM
Serial communications
data input for the main
CPU
I 0.6
72 TFT SI/
TFT DATA
Serial communications
data output for the
main CPU
O 0.4
73 Touch SW Switch output for touch
panel SW detection
O 4.1
74 NC NC(OPEN) - -
75 NC NC(OPEN) - -
76 NC NC(OPEN) - -
77 NC NC(OPEN) - -
78 NC NC(OPEN) - -
79 NC NC(OPEN) - -
80 BUS KILL For connected
confirmation of self
adjustment treatment
device
I 0
9.3. DVD Servo Block
IC501 : C1AB00002402
Pin No. Port Descriptions I/O Vol (V)
1 VDDIO I/O pad power (3.3V) - 3.3
2 MD10 SDRAM data bus I/O 0
3 MD11 SDRAM data bus I/O 0.6
4 VDD Core power (1.8V) - 1.8
5 MD12 SDRAM data bus I/O 0
6 VSSIO I/O pad ground - 0
7 MD13 SDRAM data bus I/O 0.7
8 MD14 SDRAM data bus I/O 0.5
9 MD15 SDRAM data bus I/O 0
10 VDDIO I/O pad power (3.3V) - 3.3
11 /DQM1 SDRAM data byte enable O 0
12 MA9 SDRAM address bus O 0
13 MA8 SDRAM address bus O 0
14 VSSIO I/O pad ground - 0
15 MA7 SDRAM address bus O 2.3
16 MA6 SDRAM address bus O 1.9
17 VSS Core ground - 0
18 MA5 SDRAM address bus O 1.1
19 VDDIO I/O pad power (3.3V) - 3.3
20 MA4 SDRAM address bus O 2.0
21 MA3 SDRAM address bus O 2.3
22 MCLK SDRAM clock O 1.7
23 VSSIO I/O pad ground - 0
24 CKE SDRAM clock enable O 3.3
25 MA2 SDRAM address bus O 2.3
26 MA1 SDRAM address bus O 1.0
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