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Panasonic FP-E - Page 281

Panasonic FP-E
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High−level Instructions
3 − 17
Outline Copies bit data of one 16-bit area to the specified bit of another 16-bit
area.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P5 (PBTM)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F5 BTM , DT 20 , H C04 , DT 10
R0
S D
Trigger
n
10
11
ST R 0
F 5 (BTM)
DT 20
H C04
DT 10
S 16-bit equivalent constant or 16-bit area (source)
n 16-bit equivalent constant or 16-bit area (specifies source and destination bit
positions)
D 16-bit area (destination)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
S A A A A A A A A A A A A A A
n A A A A A A A A A A A A A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
F5
P5
Bit data move
(BTM)
(PBTM)
A: Available
N/A: Not Available
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