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Panasonic FP-E - Page 285

Panasonic FP-E
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High−level Instructions
3 − 21
Outline Copies hexadecimal digits at one 16-bit area to the specified digit
position in another 16-bit area.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P6 (PDGT)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10 F6 DGT, DT10, H0, DT20
S
D
Trigger
n
R0
10
11
ST R 0
F 6 (DGT)
DT 10
H0
DT 20
S 16-bit equivalent constant or 16-bit area (source)
n 16-bit equivalent constant or 16-bit area (specifies source and destination
hexadecimal digit position and number of hexadecimal digits)
D 16-bit area (destination)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
S A A A A A A A A A A A A A A
n A A A A A A A A A A A A A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Hexadecimal
digit position
····
Bit position
·····
DT10
15
000
12
0
11
000
8
1
7
010
4
0
3
100
0
1
3210
····
Bit position
·····
DT20
15
000
12
0
11
100
8
0
7
101
4
0
3
100
0
1
Hexadecimal
digit position
3210
In this example, the upper 12 bits of DT20 do not change.
The lower four bits in the data register DT10
is copied.
F6
P6
Hexadecimal digit data move
(DGT)
(PDGT)
A: Available
N/A: Not Available
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