Panasonic FP-E - Page 395

High−level Instructions
3 − 131
Outline The two specified 32−bit data are compared and the result is output to
the special internal relay.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P61 (PDCMP)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
50 F61 DCMP , DT 0 , DT 10
60
63
66
R900A
R900B
R900C
Trigger
S1 S2
Y10
Y11
Y12
R0
R0
R0
R0
50
51
60
61
62
63
64
65
66
67
68
ST R 0
F 61 (DCMP)
DT 0
DT 10
ST R 0
AN R 900A
OT Y 10
ST R 0
AN R 900B
OT Y 11
ST R 0
AN R 900C
OT Y 12
S1 32-bit equivalent constant or lower 16-bit area of 32-bit data to be compared
S2 32-bit equivalent constant or lower 16-bit area of 32-bit data to be compared
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY K H
Index
modifier
S1 A A A A A A A A A A N/A A A A
S2 A A A A A A A A A A N/A A A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
F61
P61
(PDCMP)
(DCMP)
32-bit data comparison
A: Available
N/A: Not Available
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