Panasonic FP-E - Page 488

High−level Instructions
3 − 224
Outline Shifts out non-zero data stored at the highest address of the table to
the specified area and compresses the data in the table to the higher
address.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P98 (PCMPR)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F98 CMPR , DT 0 , DT 5 , DT 10
D1
D3
Trigger
D2
R0
10
11
ST R 0
F98 (CMPR)
DT 0
DT 5
DT 10
D1 Starting 16-bit area of the data table
D2 Ending 16−bit area of the data table
D3 16-bit area for storing the shift−out data
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
I K H
Index
modifier
D1 N/A A A A A A A A A N/A N/A N/A A
D2 N/A A A A A A A A A N/A N/A N/A A
D3 N/A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
F98
P98
(PCMPR)
(CMPR)
Data table shift−out and compress
A: Available
N/A: Not Available
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